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參數(shù)資料
| 型號： | MK3732-22RLFTR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | 26.8 MHz, OTHER CLOCK GENERATOR, PDSO20 |
| 封裝： | 0.010 INCH, ROHS COMPLIANT, SSOP-20 |
| 文件頁數(shù)： | 2/8頁 |
| 文件大?。?/td> | 204K |
| 代理商： | MK3732-22RLFTR |
MK3732-22
BLU-RAY DISC VCXO
VCXO AND SYNTHESIZER
IDT / ICS
BLU-RAY DISC VCXO
2
MK3732-22
REV D 020906
Pin Assignment
AUDIO CLK Output Table
COMM CLK Output Table
Note 1:
S1, S0, SC have an internal pull-up resistor.
Pin Descriptions
16
1
15
2
14
X1
X2
3
13
S0
4
12
VDD
VDD
5
11
6
OE
7
VDD
8
GND
S1
VDD
GND
13.5 M
VDD
27 M
ACLK
9
10
33 M
CCLK
32.11 M
SC
20
19
18
17
20 pin (150 mil) SSOP (QSOP)
S1
0
0
1
1
S0
0
1
0
1
ACLK (MHz)
8.192
11.2896
12.288
18.4323
SC
0
1
CCLK (MHz)
26.8
24.576
Pin
Number
Pin
Name
Pin
Type
Pin Description
X1
Input
Crystal connection. Connect to 13.5 MHz fundamental mode pullable
crystal.
Select ACLK per table above. Internal pull-up.
2
S0
Input
3
VDD
Power
Connect to +3.3 V.
4
VIN
Input
VCXO voltage input. Zero to 3.3 V analog voltage for VCXO.
5
VDD
Power
Connect to +3.3 V.
6
GND
Power
Connect to ground.
7
13.5 M
Output
13.5 MHz clock output. Output tri-stated when OE is low.
8
27 M
Output
27 MHz clock output. Output tri-stated when OE is low.
9
33 M
Output
33 MHz reference clock output. Output tri-stated when OE is low.
10
32.11 M
Output
32.11 MHz clock output. Output tri-stated when OE is low.
11
SC
Input
Select CCLK per table above. Internal pull-up.
12
CCLK
Output
Communication clock output. Determined by table above.
13
ACLK
Output
Audio clock output. Determined by table above.
14
VDD
Power
Connect to +3.3 V.
15
GND
Power
Connect to ground.
16
VDD
Power
Connect to +3.3 V.
17
S1
Input
Select ACLK per table above. Internal pull-up.
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