參數(shù)資料
型號(hào): MK3724GLF
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/8頁
文件大?。?/td> 0K
描述: IC VCXO DTV/SET-TOP 16-TSSOP
標(biāo)準(zhǔn)包裝: 96
類型: PLL 時(shí)鐘合成器,VCXO
PLL: 帶旁路
輸入: 晶體
輸出: LVCMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 73.728MHz
除法器/乘法器: 無/無
電源電壓: 3.135 V ~ 3.465 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 16-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 16-TSSOP
包裝: 管件
MK3724
VCXO PLUS AUDIO CLOCK FOR STB
VCXO AND SYNTHESIZER
IDT VCXO PLUS AUDIO CLOCK FOR STB
2
MK3724
REV E 051310
Pin Assignment
Pin Descriptions
Audio Clock Select Table
12
1
11
2
10
3
9
X2
4
X1
5
VDD
6
NC
7
VDD
8
VIN
VDD
S0
27M
GND
S2
GND
ACLK
16
15
14
13
PDTS
S1
16-pin TSSOP
S2
S1
S0
ACLK (MHz)
00
0
3.072
00
1
4.096
01
0
6.144
01
1
8.192
1
0
12.288
1
0
1
24.576
1
0
33.8688
1
73.728
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
X2
Output
Crystal connection. Connect to a 27 MHz fundamental mode pullable
crystal.
2
X1
Input
Crystal connection. Connect to a 27 MHz fundamental mode pullable
crystal.
3
VDD
Power
Connect to +3.3 V.
4
VDD
Power
Connect to +3.3 V.
5
VIN
Input
Voltage input to VCXO. Changing the voltage between 0 to 3.3 V controls
the VCXO frequency.
6
GND
Power
Connect to ground.
7
GND
Power
Connect to ground.
8PDTS
Power
Power Down Tri-state. This pin powers down entire chip and tri-states the
outputs when low. Internal pull-up resistor.
9
S2
Input
Select input S2. Selects ACLK per table above. Internal pull-up resistor.
10
ACLK
Output
Audio clock output per table above.
11
GND
Power
Connect to ground.
12
27M
Output
27 MHz reference clock output.
13
S0
Input
Select input S0. Selects ACLK per table above. Internal pull-up resistor.
14
VDD
Power
Connect to +3.3 V.
15
NC
--
No connect. Do not connect anything to this pin.
16
S1
Input
Select input S1. Selects ACLK per table above. Internal pull-up resistor.
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