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參數(shù)資料
| 型號(hào)： | MK2731-03STR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 24.576 MHz, VIDEO CLOCK GENERATOR, PDSO16 |
| 封裝： | 0.150 INCH, SOIC-16 |
| 文件頁(yè)數(shù)： | 3/4頁(yè) |
| 文件大小： | 61K |
| 代理商： | MK2731-03STR |
MK2731-03C
MPEG Audio Clock Synthesizer
MDS 2731-03C D
3
Revision 011101
Integrated Circuit Systems, Inc. 525 Race Street, San Jose, CA, 95126 (408) 295-9800 tel www.icst.com
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
7
V
Inputs and Clock Outputs
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless noted)
Operating Voltage, VDD
3.13
5.50
V
Input High Voltage, VIH, X1 pin only
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, X1 pin only
VDD/2
(VDD/2)-1
V
Input High Voltage, VIH
2
V
Input Low Voltage, VIL
0.8
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
Output High Voltage, VOH, CMOS level
IOH=-8mA
VDD-0.4
V
Operating Supply Current, IDD
No Load
25
mA
Short Circuit Current
Each output
±100
mA
Input Capacitance
S2, S1, S0
7
pF
Frequency synthesis error
All clocks
0
ppm
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Crystal or Clock Frequency
27.00
MHz
Input Crystal Accuracy
±30
ppm
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
60
%
Maximum Absolute Jitter, short term
see table on following page
Electrical Specifications
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
External Components
The MK2731-03 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.1F should be connected between VDD and GND on pins 3 and 5, as close to the
MK2731-03 as possible. A series termination resistor of 33
may be used for each clock output. The input
crystal must be connected as close to the chip as possible. The input crystal should be a parallel resonant,
fundamental, AT cut 27 MHz. For accurate tuning of the output when a crystal input is used, capacitors
should be connected between X1 and ground, and X2 and ground. The value of these capacitors is given by
the following equation, where CL is the crystal load capacitance: Crystal caps (pF) = (CL-10) x 2. So for a
crystal with 16 pF load capacitance, two 12 pF caps can be used.
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相關(guān)代理商/技術(shù)參數(shù) |
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| MK2731-04C | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock |
| MK2731-04S | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock |
| MK2731-04STR | 制造商:ICS 制造商全稱:ICS 功能描述:MPEG Audio Clock |
| MK2732-05 | 制造商:ICS 制造商全稱:ICS 功能描述:Low Phase Noise VCXO+Multiplier |
| MK2732-05S | 制造商:ICS 制造商全稱:ICS 功能描述:Low Phase Noise VCXO+Multiplier |
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