F
參數(shù)資料
型號(hào): MK2716SLFTR
廠商: IDT, Integrated Device Technology Inc
文件頁數(shù): 2/6頁
文件大?。?/td> 0K
描述: IC CLK SYNTHESIZER HDTV 8-SOIC
標(biāo)準(zhǔn)包裝: 2,500
類型: 時(shí)鐘合成器 - 視頻
PLL:
輸入: 時(shí)鐘,晶體
輸出: CMOS
電路數(shù): 1
比率 - 輸入:輸出: 1:2
差分 - 輸入:輸出: 無/無
頻率 - 最大: 74.25MHz
除法器/乘法器: 無/無
電源電壓: 3 V ~ 5.5 V
工作溫度: 0°C ~ 70°C
安裝類型: 表面貼裝
封裝/外殼: 8-SOIC(0.154",3.90mm 寬)
供應(yīng)商設(shè)備封裝: 8-SOIC
包裝: 帶卷 (TR)
MK2716
HDTV CLOCK SYNTHESIZER
CLOCK SYNTHESIZER
IDT HDTV CLOCK SYNTHESIZER
2
MK2716
REV G 051310
Pin Assignment
FREQUENCY SELECT TABLE
Pin Descriptions
External Components
Decoupling Capacitor
As with any high performance mixed-signal IC, the MK2716
must be isolated from system power supply noise to perform
optimally.
A decoupling capacitor of 0.01F must be connected
between VDD and GND on pins 2 and 3. It must be
connected close to the MK2716 to minimize lead
inductance. Pin 5 can be connected to pin 3. No external
power supply filtering is required for the MK2716.
Series Termination Resistor
A 33
terminating resistor can be used next to the clock
outputs for trace lengths over one inch.
Crystal Load Capacitors
The total on-chip capacitance is approximately 18 pF. A
parallel resonant, fundamental mode, AT cut 27 MHz crystal
should be used. The device crystal connections should
include pads for small capacitors from X1 to ground and
from X2 to ground. These capacitors are used to adjust the
stray capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming process,
it is important to keep stray capacitance to a minimum by
using very short PCB traces (and no vias) between the
crystal and device. Crystal capacitors, if needed, must be
connected from each of the pins X1 and X2 to ground.
The value (in pF) of these crystal caps should equal (CL -16
pF)*2. In this equation, CL= crystal load capacitance in pF.
Example: For a crystal with an 18 pF load capacitance, each
crystal capacitor would be 4 pF [(18-16) x 2] = 4.
ICLK/X1
VDD
GND
27M
CLK
SEL
GND
X2
1
2
3
4
8
7
6
5
SEL
CLK (MHz)
0
74.17582418
1
74.25
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
ICLK/X1
XI
Crystal connection. Connect to a 27 MHz fundamental crystal or clock.
2
VDD
Power
Connect to +3.3 V or +5 V.
3
GND
Power
Connect to ground.
4
27M
Output
74.17582418 MHZ or 74.25 MHz clock output (see table above).
5
GND
Power
Connect to ground.
6
SEL
Input
Select pin determines value of CLK per table above.
7
27M
Output
27 MHz buffered clock or crystal oscillator output.
8
X2
XO
Crystal connection. Connect to a 27 MHz crystal, or leave unconnected
for clock input.
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