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參數(shù)資料
| 型號(hào)： | MK2011SLFTR |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 50 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁(yè)數(shù)： | 2/4頁(yè) |
| 文件大小： | 45K |
| 代理商： | MK2011SLFTR |
MK2011
Fast Ethernet Clock Source
MDS2011B
2
Revision 12057
Printed 12/5/97
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
ICRO
CLOCK
Number
Name
Type
Description
1
X1/ICLK
I
Crystal Connection. Connect to a 20.000 MHz crystal or clock.
2
VDD
P
Connect to +5V.
3
GND
P
Connect to ground.
4
25M
O
25.000 MHz clock output.
5
50M
O
50.000 MHz clock output.
6
GND
P
Connect to ground.
7
20M
O
20.000 MHz buffered crystal clock output.
8
X2
O
Crystal Connection to a 20.000 MHz crystal, or leave unconnected for clock input.
Pin Descriptions
Key: I = Input, O = output, P = power supply connection
Pin Assignment
20.00 MHz in
(crystal caps not
shown)
Pin 1
33
(optional)
2
3
5
6
7
0.1F
25MHz out
50MHz out
G
V
33
(optional)
Suggested Layout
4
8
External Components/Crystal Selection
A minimum number of external components are required for proper oscillation. For a crystal input, one
22pF load capacitor should be connected to each of the X1 and X2 pins and ground, and a parallel
resonant 20.000 MHz, 16pF load, crystal is recommended. The frequency tolerance of the crystal should
be 50ppm or better. For a clock input, connect to X1 and leave X2 unconnected. A decoupling capacitor of
0.1F should be connected between VDD and GND on pins 2 and 3, and 33
terminating resistors
should be used on clock outputs with traces longer than 1 inch.
33
(optional)
20MHz
out
1
8
2
3
4
7
6
5
X1/ICLK
20M
GND
X2
VDD
GND
50M
8 pin SOIC
25M
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