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參數(shù)資料
| 型號： | MK1716-01RTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 1/9頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLK SOURCE SER PROGR 28-QSOP |
| 產(chǎn)品變化通告： | Product Discontinuation 13/May/2009 |
| 標準包裝： | 2,500 |
| 系列： | VersaClock™ |
| 類型： | 時鐘/頻率合成器 |
| PLL： | 是 |
| 輸入： | 時鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:9 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 133.33MHz |
| 除法器/乘法器： | 無/是 |
| 電源電壓： | 3 V ~ 3.6 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 28-QSOP |
| 包裝： | 帶卷 (TR) |
DATASHEET
SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
MK1716-01
IDT SERIAL PROGRAMMABLE PCI SS VERSACLOCK SYNTHESIZER
1
MK1716-01
REV H 051310
Description
The MK1716-01 is a versatile serial programmable clock
source which takes up very little board space.
The device can simultaneously generate two groups of 4
output clocks and a reference clock output. Both clock
groups (CLKA and CLKB) are derived from a single PLL,
and have the ability to incorporate Spread Spectrum
frequency modulation for reduced system EMI. Each group
has control of independent PLL output divide values.
Outputs may be programmed on the fly, and will lock to a
new frequency in 10 ms or less.
Each of the two groups are powered by a separate VDDIO
voltage. The reference clock uses the fixed VDD voltage.
VDDIO may vary from 2.5 V to VDD.
The devices includes a OE pin which tri-states the output
clocks and when tied low.
IDT’s VersaClockTM software allows the user to generate
MK1716-01 device optimizing configuration code for target
output frequencies and spread spectrum amounts.
Features
Packaged in 28-pin SSOP
Operating voltage 3.3 V
Serially programmable: user determines the output
frequency via a 3-wire interface
Highly accurate frequency generation
M/N Multiplier PLL: M = 1..2048, N = 1..1024
Eliminates the need for custom Quartz Oscillators
Input crystal frequency of 5-27 MHz
Input clock frequency of 3-50 MHz
Output clock frequencies of 250 kHz to 133.33 MHz
Spread Spectrum frequency modulation for reduced
system EMI
Center or down spread ±0.5% min to 4% total
Selectable 32 kHz and 120 kHz modulation rate
Advanced, low power, sub-micron CMOS process
Separate VDD ‘s for each bank of 4 outputs
Output skew <250 ps within output bank
OE control on outputs
Block Diagram
Clock
Buffer/
Crystal
Ocsillator
VDD
GND
PLL
with
Spread
SpectrumCircuit
REF OUT
CLKA
CLKB
VDDIOA
VDDIOB
DIV A
DIV B
OE
4
6
X2
Crystal or
clock input
External capacitors are
required with a crystal input.
X1/ICLK
SCLK
DATA
STROBE
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