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參數(shù)資料
| 型號(hào)： | MK1581-01GITR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | XO, clock |
| 英文描述： | LOW PHASE NOISE T1/E1 CLOCK GENERATOR |
| 中文描述： | 2.048 MHz, OTHER CLOCK GENERATOR, PDSO16 |
| 封裝： | 4.40 MM, 0.65 MM PITCH, MO-153, TSSOP-16 |
| 文件頁數(shù)： | 1/11頁 |
| 文件大?。?/td> | 183K |
| 代理商： | MK1581-01GITR |
DATASHEET
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
MK1581-01
IDT / ICS
LOW PHASE NOISE T1/E1 CLOCK GENERATOR
1
MK1581-01
REV D 073007
Description
The MK1581-01 provides synchronization and timing
control for T1 and E1 based network access or multitrunk
telecommunication systems. The device accepts an 8 kHz
frame clock input and uses an on-chip VCXO to produce a
synchronized low phase noise clock output.
This monolithic IC, combined with an external inexpensive
quartz crystal, can be used to replace a more costly hybrid
VCXO retiming module. Through selection of external loop
filter components values, the device can be tailored to meet
the system’s clock jitter attenuation requirements. Low-pass
jitter attenuation characteristics in the Hz range are
possible.
Features
Generates a T1 (1.544 MHz) or E1 (2.048 MHz) output
clock from an 8kHz frame clock input
Configurable jitter attenuation characteristics, excellent
for use as a Stratum source de-jitter circuit
VCXO-based clock generation ensures very low jitter and
phase noise generation
Output clock is phase and frequency locked to the input
reference clock
+115ppm minimum crystal frequency pullability range,
using recommended crystal
Industrial temperature range
Low power CMOS technology
16 pin TSSOP package
Single 3.3 V power supply
Block Diagram
Charge
Pump
VCXO
Pullable Crystal
Output
Divider
Feedback
Divider
8kHz_IN
CLK
X2
X1
ISET
VDD
3
VDD
VIN
CHGP
5
GND
SEL
Phase
Detector
C
P
C
S
R
S
R
SET
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MK3807-01 | BUFFER/CLOCK DRIVER |
| MK3807-01RI | BUFFER/CLOCK DRIVER |
| MK3807-01RILF | BUFFER/CLOCK DRIVER |
| MK3807-01RILFTR | BUFFER/CLOCK DRIVER |
| MK3807-01RITR | BUFFER/CLOCK DRIVER |
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