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參數(shù)資料
| 型號(hào)： | MK1575-01GILFTR |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 13/14頁 |
| 文件大小： | 0K |
| 描述： | IC CLK RECOVERY PLL 16-TSSOP |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 類型： | 時(shí)鐘和數(shù)據(jù)恢復(fù)（CDR），多路復(fù)用器 |
| PLL： | 是 |
| 主要目的： | 視頻 |
| 輸入： | 時(shí)鐘 |
| 輸出： | LVCMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:2 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 80MHz |
| 電源電壓： | 3.15 V ~ 3.45 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-TSSOP（0.173"，4.40mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-TSSOP |
| 包裝： | 帶卷 (TR) |
MK1575-01
CLOCK RECOVERY PLL
CLOCK SYNTHESIZER
IDT CLOCK RECOVERY PLL
8
MK1575-01
REV P 051310
This above set of requirements is served by the circuit
illustrated in the Optimum Power Supply Connection, below.
The main features of this circuit are as follows:
Only one connection is made to the PCB power plane.
The capacitors and ferrite chip (or ferrite bead) on the
common device supply form a lowpass ‘pi’ filter that
remove noise from the power supply as well as clock
noise back toward the supply. The bulk capacitor should
be a tantalum type, 1
μF minimum. The other capacitors
should be ceramic type.
The power supply traces to the individual VDD pins
should fan out at the common supply filter to reduce
interaction between the device circuit blocks.
The decoupling capacitors at the VDD pins should be
ceramic type and should be as close to the VDD pin as
possible. There should be no vias between the
decoupling capacitor and the supply pin.
Optimum Power Supply Connection
Series Termination Resistor
Output clock PCB traces over 1 inch should use series
termination to maintain clock signal integrity and to reduce
EMI. To series terminate a 50
Ω trace, which is a commonly
used PCB trace impedance, place a 33
Ω resistor in series
with the clock line as close to the clock output pin as
possible. The nominal impedance of the clock output is 20
Ω.
PCB Layout Recommendations
For optimum device performance and lowest output phase
noise, the following printed circuit board layout
recommendations should be observed.
1) Each 0.01F power supply decoupling capacitor should
be mounted as close to the VDD pin as possible. The PCB
trace to VDD pin should be kept as short as possible, as
should the PCB trace to the ground via. Distance of the
ferrite chip and bulk decoupling from the device is less
critical.
2) The loop filter components (RZ, CS and CB) must also be
placed close to the CHGP and VIN pins. CB should be
closest to the device. Coupling of noise from other system
signal traces should be minimized by keeping traces short
and away from active signal traces. Use of vias should be
avoided.
3) To minimize EMI the 33
Ω series termination resistor, if
needed, should be placed close to the clock output.
4) Because each input selection pin includes an internal
pull-up device, those inputs requiring a logic high state (“1”)
can be left unconnected. The pins requiring a logic low state
(“0”) can be grounded.
Loss of Reference Clock
If a loss occurs on the REFIN clock, the output frequency
will decrease at a rate of
where:
C = C1 + C2
VS = value of VS divider (from the table on page 3)
If the input is held low, the output will stop high or low, or
might toggle at several Hz.
Low Frequency Operation
The output frequency can be extended below 1.5 MHz by
adding a divider in the output path. In this configuration, it is
desirable to take the feedback signal from CLK1 rather than
the output of the divider. However, if zero delay operation is
required, the feedback signal must come from the divider
output.
Connection Via to 3.3V
Power Plane
Ferrite
Chip
0.
1
F
BULK
1
nF
VDDA
Pin
0.
01
F
VDDD
Pin
0.
01
F
10
Ω
df
dt
4250
C x VS
=
Hz/s
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1575-01GITR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1575-01GLF | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GLFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 CLOCK RECOVERY PLL RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1575-01GTR | 功能描述:IC CLK RECOVERY PLL 16-TSSOP RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 專用 系列:- 標(biāo)準(zhǔn)包裝:1,500 系列:- 類型:時(shí)鐘緩沖器/驅(qū)動(dòng)器 PLL:是 主要目的:- 輸入:- 輸出:- 電路數(shù):- 比率 - 輸入:輸出:- 差分 - 輸入:輸出:- 頻率 - 最大:- 電源電壓:3.3V 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-SSOP（0.209"，5.30mm 寬） 供應(yīng)商設(shè)備封裝:28-SSOP 包裝:帶卷 (TR) 其它名稱:93786AFT |
| MK1581-01 | 制造商:IDT 制造商全稱:Integrated Device Technology 功能描述:LOW PHASE NOISE T1/E1 CLOCK GENERATOR |
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