參數(shù)資料
型號(hào): MK1574-01ASLFTR
元件分類: 時(shí)鐘及定時(shí)
英文描述: 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
封裝: 0.150 INCH, SOIC-16
文件頁數(shù): 8/10頁
文件大小: 146K
代理商: MK1574-01ASLFTR
FRAME RATE COMMUNICATIONS PLL
MDS 1574-01A/B B
7
Revision 051206
Integrated Circuit Systems l 525 Race Street, San Jose, CA 95126 l tel (408) 297-1201 l
www.icst.com
MK1574-01A/B
Loop Bandwidth and Loop Filter Component Selection
The series-connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the
dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore a
high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine
the dynamic characteristics of the phase-locked loop. The capacitor must have very low leakage, therefore
a high quality ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic
capacitor. Ceramic capacitors should have C0G or NP0 dielectric. Avoid high-K dielectrics like Z5U and
X7R; these and other ceramics which have piezoelectric properties allow mechanical vibration in the
system to increase the output jitter because the mechanical energy is converted directly to voltage noise
on the VCO input.
The values of the RC network determine the bandwidth of the PLL. The values of the loop filter
components are calculated using the constants K1 and K2 from the Loop Filter Constants table (page 7).
The loop bandwidth is set by the capacitor C and the constant K1 using the formula:
The loop damping is set by the resistor R, the capacitor C, and the constant K2 using the formula::
For example, to design the loop filter whewn generating 8.192 MHz from 8 kHz:
1. From the Output Clock Decoding table (page 2), the address is E. The Loop Filter Constants table (page
7) shows the constants K1 = 0.0516 and K2 = 6.2.
2. A good value for the loop bandwidth is 1/20 the input frequency; where 8 kHz/20 = 400 Hz. Using
equation 1,
Therefore,
3. A good value for the damping factor
ζ is 0.707. From equation 2,
BW (Hz) =
C
K1
Equation 1
R =
Equation 2;
ζ (zeta) is the damping factor
C
ζ * K2
C
K1
400 =
C
K1
C =
400
0.0516
(
) 2
= 16.6 nF (16 nF nearest standard value
R =
= 34.7 k
(36 k nearest standard value)
16E-9
0.707 * 6.2
相關(guān)PDF資料
PDF描述
MK1574-01BSTRLF 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASTR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01ASITR 1574 SERIES, PLL BASED CLOCK DRIVER, 4 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16
MK1574-01SLFTR PLL BASED CLOCK DRIVER, PDSO16
MK1574-01S PLL BASED CLOCK DRIVER, PDSO16
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