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參數(shù)資料
| 型號： | MK1449STR |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類： | 時鐘產(chǎn)生/分配 |
| 英文描述： | 24.576 MHz, OTHER CLOCK GENERATOR, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 3/4頁 |
| 文件大?。?/td> | 40K |
| 代理商： | MK1449STR |
MK1449C
Sound Clock
MDS 1449C A
3
Revision 060198
Printed 11/15/00
MicroClock Division of ICS1271 Parkmoor Ave.San JoseCA95126(408)295-9800tel(408)295-9818fax
PRELIMINARY
PRELIMINARY INFORMATION
INFORMATION
I C R O
C LOC K
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Referenced to GND
7
V
Inputs
Referenced to GND
-0.5
VDD+0.5
V
Clock Output
Referenced to GND
-0.5
VDD+0.5
V
Ambient Operating Temperature
0
70
°C
Soldering Temperature
Max of 10 seconds
260
°C
Storage temperature
-65
150
°C
DC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Operating Voltage, VDD
3
5.5
V
Input High Voltage, VIH, ICLK only
ICLK (Pin 1)
(VDD/2)+1
VDD/2
V
Input Low Voltage, VIL, ICLK only
ICLK (Pin 1)
VDD/2
(VDD/2)-1
V
Output High Voltage, VOH
IOH=-25mA
2.4
V
Output Low Voltage, VOL
IOL=25mA
0.4
V
IDD Operating Supply Current
No Load
18
mA
IDD Operating Supply Current, 3.3V
No Load
10
mA
Short Circuit Current
24.576 MHz outputs
±70
mA
AC CHARACTERISTICS (VDD = 5.0V unless otherwise noted)
Input Frequency, crystal input
14.31818
MHz
Input Frequency, clock input
14.31818
MHz
Output Frequency
VDD = 3.0 to 5.5V
24.576
MHz
Output Clock Rise Time
0.8 to 2.0V
1
ns
Output Clock Fall Time
2.0 to 0.8V
1
ns
Output Clock Duty Cycle
at VDD/2
45
49 to 51
55
%
Synthesis error
1
ppm
Absolute Clock Period Jitter
Deviation from mean
±120
ps
One Sigma Clock Period Jitter
50
ps
Electrical Specifications
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