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參數(shù)資料
| 型號(hào)： | MK1413SLF |
| 廠商： | IDT, Integrated Device Technology Inc |
| 文件頁數(shù)： | 3/7頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC AUDIO CLK SOURCE MPEG 8-SOIC |
| 標(biāo)準(zhǔn)包裝： | 97 |
| 類型： | 時(shí)鐘合成器 - 音頻 |
| PLL： | 是 |
| 輸入： | 時(shí)鐘，晶體 |
| 輸出： | CMOS |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 1:1 |
| 差分 - 輸入:輸出： | 無/無 |
| 頻率 - 最大： | 16.9344MHz |
| 除法器/乘法器： | 無/無 |
| 電源電壓： | 3 V ~ 5.5 V |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 8-SOIC |
| 包裝： | 管件 |
MK1413
MPEG AUDIO CLOCK SOURCE
CLOCK SYNTHESIZER
IDT / ICS MPEG AUDIO CLOCK SOURCE
3
MK1413
REV G 051310
Application Information
Series Termination Resistor
Clock output traces should use series termination. For
series terminating a 50
trace (a commonly used trace
impedance), place a 33
resistor in series with the clock line
and as close to the clock output pin as possible. The
nominal impedance of the clock output is 20
.
Crystal Load Capacitors
The device crystal connections should include pads for
capacitors from X1 to ground and from X2 to ground, and a
parallel rsonant 14.31818 MHz crystal is recommended.
These capacitors are used to adjust the stray capacitance of
the board to match the nominally required crystal load
capacitance. To reduce possible noise pickup, use very
short PCB traces (and no vias) been the crystal and device.
The value (in pF) of each crystal load capacitor should equal
(CL -4) x2, where CL is the crystal’s load (correlation)
capacitance in pF. The frequency tolerance of the crystal
should be 50 ppm or better.For a clock input, connect X1
and leave X2 unconnected. Because these capacitors
adjust the stray capacitance of the PCB, check the output
frequency using your final layout to see if the value of C
should be changed.
PCB Layout Recommendations
Observe the following guidelines for optimum device
performance and lowest output phase noise:
1) Each 0.01F decoupling capacitor should be mounted on
the component side of the board as close to the VDD pin as
possible. No vias should be used between decoupling
capacitor and VDD pin. The PCB trace to VDD pin should
be kept as short as possible, as should the PCB trace to the
ground via. Distance of the ferrite bead and bulk decoupling
from the device is less critical.
2) The external crystal should be mounted next to the device
with short traces. The X1 and X2 traces should not be
routed next to each other with minimum spaces, instead
they should be separated and away from other traces.
3) To minimize EMI, and obtain the best signal integrity, the
33
series termination resistor should be placed close to
the clock output.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other signal
layers (the ferrite bead and bulk decoupling capacitor can be
mounted on the back). Other signal traces should be routed
away from the MK1413. This includes signal traces just
underneath the device, or on layers adjacent to the ground
plane layer used by the device.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MK1413SLFTR | 功能描述:時(shí)鐘發(fā)生器及支持產(chǎn)品 MPEG AUDIO CLOCK SOURCE RoHS:否 制造商:Silicon Labs 類型:Clock Generators 最大輸入頻率:14.318 MHz 最大輸出頻率:166 MHz 輸出端數(shù)量:16 占空比 - 最大:55 % 工作電源電壓:3.3 V 工作電源電流:1 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:QFN-56 |
| MK1413STR | 功能描述:IC AUDIO CLK SOURCE MPEG 8-SOIC RoHS:否 類別:集成電路 (IC) >> 時(shí)鐘/計(jì)時(shí) - 時(shí)鐘發(fā)生器，PLL，頻率合成器 系列:- 標(biāo)準(zhǔn)包裝:39 系列:- 類型:* PLL:帶旁路 輸入:時(shí)鐘 輸出:時(shí)鐘 電路數(shù):1 比率 - 輸入:輸出:1:10 差分 - 輸入:輸出:是/是 頻率 - 最大:170MHz 除法器/乘法器:無/無 電源電壓:2.375 V ~ 3.465 V 工作溫度:0°C ~ 70°C 安裝類型:* 封裝/外殼:* 供應(yīng)商設(shè)備封裝:* 包裝:* |
| MK1418 | 制造商:ICS 制造商全稱:ICS 功能描述:OPL3, OPL4 + Codec Clock Source |
| MK1418S | 制造商:ICS 功能描述: |
| MK1418STR | 制造商:ICS 制造商全稱:ICS 功能描述:OPL3, OPL4 + Codec Clock Source |
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