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參數(shù)資料
| 型號(hào)： | MIC74YQS |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 3/18頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16QSOP |
| 標(biāo)準(zhǔn)包裝： | 98 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數(shù)： | 8 |
| 中斷輸出： | 是 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應(yīng)商設(shè)備封裝： | 16-QSOP |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 1083 (CN2011-ZH PDF) |
| 其它名稱： | 576-1958-5 MIC74YQS-ND |
Micrel, Inc.
MIC74
October 2006
11
M9999-101006
Application Information
Bit Transfer
The data received on the DATA pin must be stable
during the high period of the clock.
DATA
CLK
Data Change Allowed
Data Stable,
Data Valid
Figure 3. Acceptable Bit Transfer Conditions
Data can change state only when the CLK line is low.
Refer to Figure 3.
Start and Stop Conditions
Two unique bus situations define “start” and “stop”
conditions. A high-to-low transition of the DATA line
while CLK is high indicates a start condition. A low-to-
high transition of the DATA line while CLK is high
defines a stop condition. See Figure 4.
DATA
CLK
S
tart
StoP
Figure 4. Start and Stop Definitions
Start (S) and stop (P) conditions are always generated
by the bus master (host). After a start condition, the bus
is considered to be busy. The bus becomes free again
after a certain time following a stop condition or after
both CLK and DATA lines remain high for more than
50s.
Serial Byte Format
Every byte consists of 8 bits. Each byte transferred on
the bus must be followed by an acknowledge bit. Bytes
are transferred with the MSB (most significant bit) first.
See Figure 5.
123456789
12345678
9
ACK
MSB
LSB
DATA
CLK
Byte Complete
S
tart
StoP
Figure 5. Serial Byte Format
Acknowledge and Not Acknowledge
The acknowledge related clock pulse is generated by the
master. The transmitter releases the DATA line (high)
during the acknowledge clock cycle.
In order to acknowledge (ACK) a byte, the receiver must
pull the DATA line low during the high period of the clock
pulse according the bus timing specifications. A slave
device that wishes to not acknowledge a byte must let
the DATA line remain high during the acknowledge clock
pulse. See Figure 6.
12
345
6789
ACK
MSB
LSB
NAK (high)
ACK (low)
DATA
(Host)
CLK
DATA
(Slave MIC74)
Figure 6. Acknowledge and Not Acknowledge
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