參數資料
| 型號： | MIC74BQS TR |
| 廠商： | Micrel Inc |
| 文件頁數： | 4/18頁 |
| 文件大小： | 0K |
| 描述： | IC I/O EXPANDER I2C 8B 16QSOP |
| 標準包裝： | 2,500 |
| 接口： | I²C，SM 總線 |
| 輸入/輸出數： | 8 |
| 中斷輸出： | 是 |
| 電源電壓： | 2.7 V ~ 3.6 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SSOP（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 16-QSOP |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC74BQSTR MIC74BQSTR-ND |
Micrel, Inc.
MIC74
October 2006
12
M9999-101006
S 00011001 A 0100 A2 A1 A0 0/A P
Alert Response Address
(master requests address
of interupting device)
P0*
/ALERT
Slave Address
(interrupting MIC74
announces its address)
Master-to-slave transmission
Slave-to-master response
STOP
ACKNOWLEDGE
R/W = READ
NOT ACKNOWLEDGE
t/INT
t/IR
*Assumes P0 interrupts properly configured and
enabled. P0 used as an example. Timing for P1
to P7 is identical.
Figure 7. Interrupt Handling Using the Alert Response Address
/A P
S0 0 0 1 A2 A1 A0 0 A 0 0 0 0 0 0
XXXXXX XX
11 A
A
Slave Address
(host addresses an MIC74)
P0*
/ALERT
Command Byte
(03h = selects status register)
Status Value
(MIC74 sends status)
Slave Address
(host addresses an MIC74)
Master-to-slave transmission
Slave-to-master response
ACKNOWLEDGE
R/W = WRITE
S 0001 A2 A1 A0 1
R/W = READ
STOP
NOT ACKNOWLEDGE
t/INT
t/R
* Assumes P0 interrupts properly configured and
enabled. P0 used as an example. Timing for P1
to P7 is identical.
STATUS register is cleared to zero following this
operation.
ACKNOWLEDGE
Figure 8. Interrupt Handling Without the Alert Response Address
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