參數(shù)資料
型號: MIC5891BN
廠商: MICREL INC
元件分類: 外設(shè)及接口
英文描述: 8-Bit Serial-Input Latched Source Driver
中文描述: SIPO BASED PRPHL DRVR, PDIP16
封裝: PLASTIC, DIP-16
文件頁數(shù): 4/4頁
文件大小: 55K
代理商: MIC5891BN
December 1997
7-57
MIC5891
Micrel
7
Applications Information
Serial data present at the input is transferred into the shift
register on the rising edge of the CLOCK input pulse. Additional
CLOCK pulses shift data information towards the SERIAL
DATA OUTPUT. The serial data must appear at the input prior
to the rising edge of the CLOCK input waveform.
The 8 bits present in the shift register are transferred to the
respective latches when the STROBE is high (serial-to-
parallel conversion). The latches will continue to accept new
Truth Table
Serial
Data
Input
Shift Register Contents
Serial
Data
Output
Latch Contents
Output Content
Clock
Input
Strobe
Input
Output
Enable
I
1
I
2
I
3
I
N-1
I
N
I
1
I
2
I
3
… I
N-1
I
n
I
1
I
2
I
3
… I
N-1
I
n
H
L
X
H
L
R
1
X
P
1
R
1
R
1
R
2
X
P
2
R
2
R
2
R
3
X
P
3
R
N-2
R
N-1
R
N-2
R
N-1
R
N-1
R
N
X
P
N-1
P
N
R
N-1
R
N-1
R
N
X
P
N
X
L
H
R
1
P
1
X
R
2
P
2
X
R
3
P
3
X
… R
N-1
R
N
… P
N-1
P
N
X
L
H
P
1
P
2
P
3
… P
N-1
P
N
L
L
L …
X
L
L
L = Low Logic Level
H = High Logic Level
X = Irrelevant
P = Present State
R = Previous State
CLOCK
DATA IN
STROBE
OUTPUT
ENABLE
OUTN
B
D
F
E
C
G
A
H
I
Timing Conditions
data as long as the STROBE is held high. Most applications
where the latching feature is not used (STROBE tied high)
require the OUTPUT ENABLE input to be high during serial
data entry.
Outputs are active (controlled by the latch state) when the
OUTPUT ENABLE is low. All Outputs are low (disabled) when
the OUTPUT ENABLE is high. OUTPUT ENABLE does not
affect the data in the shift register or latch.
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