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參數(shù)資料
| 型號： | MIC5190 |
| 廠商： | Micrel Semiconductor,Inc. |
| 英文描述： | ECONOLINE: RY & RX - Controllable Output- 1kVDC Isolation- No Heatsink Required- UL94V-0 Package Material- Toroidal Magnetics- No External Components- Fully Encapsulated- Efficiency to 70% |
| 中文描述： | 超高速，高電流有源濾波器/ LDO控制器 |
| 文件頁數(shù)： | 7/13頁 |
| 文件大?。?/td> | 169K |
| 代理商： | MIC5190 |
April, 2
00
4
7
M9999-
0
428
0
4
M
IC
5
1
9
0
Applications Information
Designing with the MIC5190
Anatomy of a transient response
T
he measure of a regulator is how accurately and effectively
it can maintain a set output voltage, regardless of the load's
power demands.
O
ne measure of regulator response is the
load step.
T
he load step gauges how the regulator responds
to a change in load current. Figure 2 is a look at the transient
response to a load step.
Micrel
Figure 2. Typical Transient Response
At the start of a circuit's power demand, the output voltage is
regulated to its set point, while the load current runs at a
constant rate. For many different reasons, a load may ask for
more current without warning. When this happens, the regu-
lator needs some time to determine the output voltage drop.
T
his is determined by the speed of the control loop.
S
o, until
enough time has elapsed, the control loop is oblivious to the
voltage change.
T
he output capacitor must bear the burden
of maintaining the output voltage.
S
ince this is a sudden change in voltage, the capacitor will try
to maintain voltage by discharging current to the output.
T
he
first voltage drop is due to the output capacitor's E
S
L (equiva-
lent series inductance).
T
he E
S
L will resist a sudden change
in current from the capacitor and drop the voltage quickly.
T
he
amount of voltage drop during this time will be proportional to
the output capacitor's E
S
L and the speed at which the load
steps.
S
lower load current transients will reduce this effect.
P
lacing multiple small capacitors with low E
S
L in parallel can
help reduce the total E
S
L and reduce voltage droop during
high speed transients. For high speed transients, the greatest
voltage deviation will generally be caused by output capacitor
E
S
L and parasitic inductance.
After the current has overcome the effects of the E
S
L, the
output voltage will begin to drop proportionally to time and
inversely proportional to output capacitance.
O
utput voltage variation will depend on two factors: loop
bandwidth and output capacitance.
T
he output capacitance
will determine how far the voltage will fall over a given time.
With more capacitance, the drop in voltage will fall at a
decreased rate.
T
his is the reason that more capacitance
provides a better transient response for the same given
bandwidth.
T
he time it takes for the regulator to respond is directly
proportional to its bandwidth gain. Higher bandwidth control
loops respond quicker causing a reduced drop on the supply
for the same amount of capacitance.
Final recovery back to the regulated voltage is the final phase
of transient response and the most important factors are gain
and time. Higher gain at higher frequency will get the output
voltage closer to its regulation point quicker.
T
he final settling
point will be determined by the load regulation, which is
proportional to
DC
(
0
Hz) gain and the associated loss terms.
T
here are other factors that contribute to large signal tran-
sient response, such as source impedance, phase margin,
and
PSRR
. For example, if the input voltage drops due to
source impedance during a load transient, this will contribute
to the output voltage deviation by filtering through to the
output reduced by the loops
PSRR
at the frequency of the
voltage transient.
I
t is straightforward: good input capaci-
tance reduces the source impedance at high frequencies.
Having between
3
5
°
and 45
°
of phase margin will help speed
up the recovery time.
T
his is caused by the initial overshoot
in response to the loop sensing a low voltage.
Compensation
T
he M
IC
5
1
9
0
has the ability to externally control gain and
bandwidth.
T
his allows the M
IC
5
1
9
0
design to be individually
tailored for different applications.
I
n designing the M
IC
5
1
9
0
, it is important to maintain ad-
equate phase margin.
T
his is generally achieved by having
the gain cross the
0
dB point with a single pole 2
0
dB/decade
roll-off.
T
he compensation pin is configured as Figure
3
demonstrates.
Error Amplifier
D
river
3
.42M
2
0
pF
I
nternal
External
C
omp
Figure 3. Internal Compensation
V
Ldi
dt
=
V
C
idt
=
∫
1
V
C
idt
↓=
↑
∫
1
V
C
idt
↓=
∫
↓
1
V
L
di
dt
↓=
↑
V
L
di
dt
↓=
↓
T
ime
∫
idt
C
V =
1
BW
1
L
C
u
O
u
V
o
A
C
-
C
o
O
utput voltage vs. time
during recovery is
directly proportional to
gain vs. frequency.
V
=
L
di
dt
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