參數(shù)資料
型號: MIC3001BML
廠商: Micrel Inc
文件頁數(shù): 5/76頁
文件大?。?/td> 0K
描述: IC FOM MANAGEMENT W/CALIBR 24MLF
標準包裝: 75
類型: 收發(fā)器
規(guī)程: SDHj Sonet
電源電壓: 3 V ~ 3.6 V
安裝類型: 表面貼裝
封裝/外殼: 24-VFQFN 裸露焊盤,24-MLF?
供應商設備封裝: 24-MLF?(4x4)
包裝: 托盤
Micrel, Inc.
MIC3001
August 2004
13
M9999-082404-A
hbwhelp@micrel.com or (408) 955-1690
Serial Data I/O Pin, Data
Symbol
Parameter
Condition
Min
Typ
Max
Units
VOL
Low Output Voltage
IOL = 3mA
0.4
V
IOL = 6mA
0.6
V
VIL
Low Input Voltage
0.8
V
VIH
High Input Voltage
2.1
V
ILEAK
Input Current
±1
A
CIN
Input Capacitance
Note 4
10
pF
Serial Clock Input, CLK
VIL
Low Input Voltage
2.7V
≤ VDD ≤ 3.6V
0.8
V
VIH
High Input Voltage
2.7V
≤ VDD ≤ 3.6V
2.1
V
ILEAK
Input Current
±1
A
CIN
Input Capacitance
Note 4
10
pF
Serial Interface Timing
(4)
t1
CLK (clock) Period
2.5
s
t2
Data In Setup Time to CLK High
100
ns
t3
Data Out Stable After CLK Low
300
ns
t4
Data Low Setup Time to CLK
Low
Start Condition
100
ns
t5
Data High Hold Time After CLK
High
Stop Condition
100
ns
tDATA
Data Ready Time
From power on to completion of one
set of ADC conversions; analog data
available via serial interface.
400
ms
Notes:
1.
Exceeding the absolute maximum rating may damage the device.
2.
The device is not guaranteed to function outside its operating rating.
3.
Devices are ESD sensitive. Handling
4.
precautions recommended.
5.
Guaranteed by designing and/or testing of related parameters. Not 100% tested in production.
6.
The MIC3000 will attempt to enter its shutdown state when VDD falls below VUVLO. This operation requires time to complete. If the supply
voltage falls too rapidly, the operation may not be completed.
7.
Does not include quantization error.
8.
The MIC3001 will not respond to serial bus transactions during an EEPROM write-cycle. The host will receive a NACK during tWR.
9.
Final test on outgoing product is performed at TA = +25°C.
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