參數(shù)資料
型號: MIC2810-1JGMYML TR
廠商: Micrel Inc
文件頁數(shù): 13/18頁
文件大?。?/td> 508K
描述: IC REG TRPL BUCK/LINEAR 16MLF
標準包裝: 5,000
拓撲: 降壓(降壓)(1),線性(LDO)(2)
功能: 任何功能
輸出數(shù): 3
頻率 - 開關: 2MHz
電壓/電流 - 輸出 1: -,600mA
電壓/電流 - 輸出 2: -,300mA
電壓/電流 - 輸出 3: -,300mA
帶 LED 驅(qū)動器:
帶監(jiān)控器:
帶序列發(fā)生器:
電源電壓: 1.65 V ~ 5.5 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 16-VFQFN,16-MLF?
供應商設備封裝: 16-MLF?(3x3)
包裝: 帶卷 (TR)
Micrel, Inc.
MIC2810
 
 
February 2008 
13
M9999-022008-C
 
Device Functional Description
The MIC2810 is a power management IC with a single
integrated step-down regulator and two low dropout
regulators. LDO1 and LDO2 are 300mA low dropout
regulators supplied from the input voltage pins. The
step-down regulator is a 600mA PWM power supply. All
three regulators utilize a /LOWQ light load mode to
maximize battery efficiency under light load conditions.
This is achieved with a /LOWQ control pin that when
pulled low shuts down all the biasing and drive current
for the PWM regulator, along with reducing the current
limit of the two independent LDOs. When the /LOWQ pin
is pulled low, the MIC2810 draws only 30礎 of operating
current. This mode allows the output to be regulated
through the LDO output which is capable of providing
60mA of output current. This method has the advantage
of producing a clean, low current, ultra-low noise output
in /LOWQ mode. During /LOWQ mode, the SW node
becomes high impedance, blocking current flow. Other
methods of reducing quiescent current, such as pulse
frequency modulation (PFM) or bursting techniques
create large amplitude and low frequency ripple voltages
that can be detrimental to system operation.
When more than 60mA is required, the /LOWQ pin can
be forced high, causing the MIC2810 to enter PWM
mode. In this case, the LDO output makes a "hand-off"
to the PWM regulator with virtually no variation in output
voltage. The LDO output then turns off allowing up to
600mA of current to be efficiently supplied through the
PWM output to the load.
Pin Functional Description
VIN/VIN1/VIN2
Three input voltage pins provide power to the switch
mode regulator, LDO1, and LDO2. VIN provides power
to the control circuitry of the DC/DC converter and
voltage reference circuitry shared by all the regulators in
the MIC2810. LDO1s input voltage (VIN1) can go down
to 1.65V but LDO2 and the DC/DC converter input
voltages are limited to 2.7V minimum.
For the switch mode regulator VIN provides power to the
MOSFET along with current limiting sense circuitry. Due
to the high switching speeds, a 4.7礔 capacitor is
recommended close to VIN and the power ground
(PGND) pin for bypassing. Please refer to the PCB
layout section for an example of an appropriate circuit
layout.
LDO
The LDO pin is the output of the linear regulator and
should be connected to the output of the step-down
PWM regulator. In /LOWQ mode (/LOWQ <0.2V), the
LDO provides the output voltage of the DC/DC regulator.
LDO1
Regulated output voltage of LDO1. Power is provided by
VIN1. Recommended output capacitance is 2.2礔.
LDO2
Regulated output voltage of LDO2. Power is provided by
VIN2. Recommended output capacitance is 2.2礔.
EN/EN1/EN2
All enable inputs are active high, requiring 1.0V for
guaranteed operation. EN provides logic control for the
DC/DC regulator. EN2 provides logic control for LDO2,
and EN1 provides logic control for LDO1. The enable
inputs are CMOS logic and cannot be left floating.
The enable pins provide logic level control of the
specified outputs. When all enable pins are in the off
state, supply current of the device is greatly reduced
(typically <1礎). When the DC/DC regulator is in the off
state, the output drive is placed in a "tri-stated" condition,
where both the high side P-channel MOSFET and the
low-side N-channel are in an off or non-conducting
state. Do not drive any of the enable pins above the
supply voltage.
Power-On Reset (POR)
The power-on reset output is an open-drain N-Channel
device, requiring a pull-up resistor to either the input
voltage or output voltage for proper voltage levels. The
POR output has a delay time that is programmable with
a capacitor from the CSET pin to ground. The delay time
can be programmed to be as long as 1 second.
/LOWQ
The /LOWQ pin provides a logic level control between
the internal PWM switching regulator mode, and the low
noise linear regulator mode. With /LOWQ pulled low
(d0.2V), quiescent current of the device is greatly
reduced by switching to a low noise linear regulator
mode that has a typical supply current of 38礎. In linear
(LDO) mode the output can deliver 60mA of current to
the output. By placing /LOWQ high (e1V), the device
transitions into a constant frequency PWM step-down
regulator mode. This allows the device the ability to
efficiently deliver up to 600mA of output current at the
same output voltage.
/LOWQ mode also limits the output load of both LDO1
and LDO2 to <50mA.
BIAS
The BIAS pin supplies the power to the internal control
and reference circuitry. The bias is powered from VIN
through an internal 6& resistor. A small 0.1礔 capacitor
is recommended for bypassing.
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