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參數(shù)資料
| 型號： | MIC2594-2BM TR |
| 廠商： | Micrel Inc |
| 文件頁數(shù)： | 11/21頁 |
| 文件大小： | 1079K |
| 描述： | IC CTRLR HOT SWAP NEG HV 8-SOIC |
| 標準包裝： | 2,500 |
| 類型： | 熱交換控制器 |
| 應用： | 通用 |
| 內部開關： | 無 |
| 電源電壓： | -19 V ~ -80 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 8-SOIC（0.154"，3.90mm 寬） |
| 供應商設備封裝： | 8-SOIC |
| 包裝： | 帶卷 (TR) |
| 其它名稱： | MIC2594-2BMTR MIC2594-2BMTR-ND |
MIC2588/MIC2594
Micrel
M9999-083005
11
September 2005
Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying live
supply voltages ( hot swapped ), high inrush currents often
result due to the charging of bulk capacitance that resides
across the circuit boards supply pins. These current spikes
can cause the systems supply voltages to temporarily go
out of regulation, causing data loss or system lock-up. In
more extreme cases, the transients occurring during a hot
swap event may cause permanent damage to connectors or
on-board components.
The MIC2588 and the MIC2594 are designed to address these
issues by limiting the magnitude of the transient or inrush cur-
rent during hot swap events. This is achieved by controlling
the rate at which power is applied to the circuit board (di/dt
and dv/dt management). Additionally, the MIC2588 and the
MIC2594 incorporate input voltage supervisory functions and
current limiting, thereby providing robust protection for both
the system and the circuit board.
Start-Up Cycle
When the input voltage to the controller is between the over-
voltage and undervoltage thresholds (MIC2588) or is greater
than V
ON
(MIC2594), a start cycle is initiated to deliver power
to the load. At this time, the GATE pin of the controller ap-
plies a constant charging current (I
GATEON
) to the gate of the
external MOSFET (M1). C
FDBK
creates a Miller integrator
out of the MOSFET circuit, which limits the slew-rate of the
voltage at the drain of M1. The drain voltage rate-of-change
(dv/dt) of M1 is:
dv M1
dt
I
C
I
C
DRAIN
GATE()
FDBK
GATEON
FDBK
(
)
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
where I
GATE(+)
= Gate Charging Current = I
GATEON
;
I
GATE()
E I
GATE(+)
, due to the extremely high transconduc-
tance values of power MOSFETs; and
I
C
dv M1
dt
GATE()
FDBK
DRAIN
=
?/DIV>
(
)
Relating the above to the maximum transient (or inrush) current
charging the load capacitance upon hot swap or power-up
involves an extension of the same formula:
I
C
dv M1
dt
I
C
I
C
| I
|
C
C
INRUSH
LOAD
DRAIN
INRUSH
LOAD
GATEON
FDBK
INRUSH
LOAD
GATEON
FDBK
=
?/DIV>
(
)
=
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=
碔
(1)
The presence of C3 and R
FDBK
prevent turn-on of the
external pass device by limiting the hot swap current
surges induced by AC coupled transients from the drain
to the gate of M1 (i.e., C
FDBK
+ C
GD
(M1)). An appropriate
value for C3 may be determined using the formula for a
capacitive voltage divider.
The maximum voltage on C3 at turn-on must be less than
V
THRESHOLD
of M1.
1. For a standard 10V enhancement N-Channel
MOSFET, V
THRESHOLD
is about 4.25V.
2. Choose 2V as the maximum voltage to avoid turn-
on transients.
C3 = (C
FDBK
+ C
GD
(M1)) ?
V
IN
(max) V
GS
(M1)
V
GS
(M1)
V
GS
(M1) ?[C3 + (C
FDBK
+ C
GD
(M1))] = V
IN
(max) ?(C
FDBK
+ C
GD
(M1))
V
GS
(M1) ?C3 = (V
IN
(max) V
GS
(M1))(C
FDBK
+ C
GD
(M1))
(2)
where V
IN
(max) = V
DD
V
EE
(min).
For example, we can determine appropriate capacitor values
given a hot swap controller that is required to maintain the
inrush current into a 220礔 load capacitance at 2A maximum
and an input supply voltage as high as V
IN
(max) = 75V. One
of the suggested MOSFETs to be used with the MIC2588/
MIC2594 is an SUM110N10-09,a 100V D
2
PAK device which
has a typical C
GD
of 750pF.
Calculating a value for C
FBDK
using Equation 1 yields:
C
220 F 45 A
2A
4.95nF
FDBK
=
m ?nbsp m
=
Good engineering practice suggests the use of the worst-
case parameter values for I
GATEON
from the DC Electrical
Characteristics section:
C
220 F 60 A
2A
6.6nF
FDBK
=
m ?nbsp m
=
where the nearest standard 5% value is 6.8nF. Substituting
6.8nF into Equation 2 from above yields:
C
6.8nF 750pF
75V 2V
2V
0.275 F
3 =
+
(
)
?/DIV>
(
)
=
m
For C3, the nearest standard 5% value is 0.22礔.
While the value for R
FDBK
is not critical, it should be chosen
to allow a maximum of a few milliamperes to ow in the
gate-drain circuit of M1 during turn-on. While the nal value
for R
FDBK
is determined empirically, initial values between
R
FDBK
= 15k?to 27k?for systems with a maximum value
of V
IN
(max) = 75V are appropriate.
Resistor R4, in series with the MOSFET's gate, minimizes
the potential for parasitic high frequency oscillations from
occurring in M1. While the exact value of R4 is not critical,
commonly used values for R4 range from 10?to 33?
Power-Good (PWRGD or /PWRGD) Output
For the MIC2588-1 and the MIC2594-1, the Power-Good
output signal (PWRGD) will be high impedance when
V
DRAIN
drops below V
PGTH
, and will pull down to V
DRAIN
when V
DRAIN
is above V
PGTH
. For the MIC2588-2 and the
MIC2594-2, /PWRGD will pull down to the potential of the
V
DRAIN
pin when V
DRAIN
drops below V
PGTH
, and will be
high impedance when V
DRAIN
is above V
PGTH
. Hence, the
-1 parts have an active-high PWRGD signal and the -2 parts
have an active-low /PWRGD output. Either PWRGD or
/PWRGD may be used as an enable signal for one or more
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