參數(shù)資料
型號： MIC2592B
廠商： Micrel Semiconductor,Inc.
英文描述： Dual-Slot PCI Express Hot-Plug Controller
中文描述： 雙插槽的PCI Express熱插拔控制器
文件頁數(shù)： 5/31頁
文件大?。?/td> 1916K
代理商： MIC2592B
March 2005
5
M9999-033105
MIC2592B
Pin Description (continued)
Micrel
Pin Number
Pin Name
Pin Function
controller.
short-circuit faults.
input supply is valid and stabe (i.e., t
STBY
/FAULTA and /FAULTB.
POR
input supply is valid and stabe (i.e., t
STBY
SMI power control. Also, see pin description for /FAULTA and /FAULTB.
POR
elapses - See the
FLT
for each slot. The overcurrent filter
FLT
) is the amount of time for which a slot remains in current limit
before its circuit breaker is tripped.
its respective +12V, +3.3V, and VAUX outputs. Each pin requires an external
.
STBY
.
brought low to deassert the /FAULT[A/B] output.
STBY
thermal protection for the VAUX[A/B] supplies. Additionally included are the
/FORCE_ON[A/B] pins do not disable UVLO protection for the VAUX[A/B]
pins -- See CNTRL[A/B] Register Bit D[2].
pin to GND.
threshold. Both pins must be externally connected together at the MIC2592B
400mΩ MOSFETs. These outputs are current limited and protected against
these pins to GND if using SMI power control. Also, see pin description for
the respective slot’s Aux Output Fault Latch. Tie these pins to GND if using
delay (t
pull-up resistor to V
outputs of the same slot, then both ON[A/B] and AUXEN[A/B] must be
explcitly includes all overcurrent and short circuit protections, and on-chip
to disable (unconditionally deassert) either or both of the /FORCE_ON[A/B]
38
GPI_B0
reading the Common Status Register, Bits [4:5]. If not used, connect each
prevents turn-on of this supply until VSTBY[A/B] rises above its UVLO
22
VAUXB
the 3.3AUX pin of the PCI Express connectors to VSTBY[A/B] via internal
a fault resets the +12V and/or +3.3V fault latches for the affected slot. Tie
Electrical Characteristics Table). Taking AUXEN[A/B] low after a fault resets
35
CFILTERB
pins and GND set the duration of t
31
/PWRGDB
VAUX output. If a fault condition occurred on both the MAIN and VAUX
28
/FORCE_ONB
VAUX), while specifically defeating all protections on those supplies. This
There is a pair of register bits, accessible via the SMBus, which can be set
11
26
VSTBYA
VSTBYB
3.3V Standby Input Voltage: Required to support PCI Express VAUX output.
Additionally, the SMBus logic and internal registers run off of VSTBY[A/B]
to ensure that the chip is accessible during standby modes. A UVLO circuit
15
VAUXA
3.3VAUX[A/B] Outputs to PCI Express Card Slots: These outputs connect
44
43
ONA
ONB
Enable Inputs: Rising-edge triggered. Used to enable or disable the MAINA
and MAINB (+3.3V and +12V) outputs. The outputs can be switched on by
these controls only after the V
elapses - See the Electrical Characteristics Table). Taking ON[A/B] low after
45
42
AUXENA
AUXENB
Enable Inputs: Rising-edge triggered. Used to enable or disable the
VAUX[A/B] outputs. The outputs can be switched on by these controls only
after the V
2
CFILTERA
Overcurrent Timers: Capacitors connected between these
6
/PWRGDA
/PWRGD[A/B] Outputs: Open-drain, active-low. Asserted when a slot has
been commanded to turn on and has successfully begun delivering power to
1
36
/FAULTA
/FAULTB
/FAULT[A/B] Outputs: Open-drain, active-low. Asserted whenever the
circuit breaker trips due to a fault condition (overcurrent, input undervoltage,
overtemperature). Each pin requires an external pull-up resistor to V
Bringing the slot’s ON[A/B] pin low resets /FAULT[A/B] if /FAULT[A/B]
was asserted in response to a fault condition on one of the slot’s MAIN out-
puts (+12V or +3.3V).
/FAULT[A/B] is reset by bringing the slot’s AUXEN[A/B] pin low if
/FAULT[A/B] was asserted in response to a fault condition on the slot’s
9
/FORCE_ONA
Enable Inputs: Active-low, level-sensitive. Asserting a /FORCE_ON[A/B]
input will turn on all three of the respective slot’s outputs (+12V, +3.3V, and
UVLO protections for the +3.3V and +12V main supplies. The
supplies. These input pins are intended for diagnostic purposes only.
Asserting /FORCE_ON[A/B] will cause the respective slot’s /PWRGD[A/B]
and /FAULT[A/B] pins to enter their open-drain state. Note that the SMBus
register set will continue to reflect the actual state of each slot’s supplies.
4
GPI_A0
General Purpose Inputs: The states of these two inputs are available by
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