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參數(shù)資料
| 型號： | MIC2592B-5BTQ |
| 廠商： | MICREL INC |
| 元件分類： | 電源管理 |
| 英文描述： | Dual-Slot PCI Express Hot-Plug Controller |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 17/31頁 |
| 文件大?。?/td> | 1916K |
| 代理商： | MIC2592B-5BTQ |
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March 2005
17
M9999-033105
MIC2592B
Micrel
Inrush Current and Load Dominated Start-up
The expected maximum inrush current can be calculated by
using the following equation:
C
C
GATE
INRUSH
I
25 A
C
C
GATE
LOAD
LOAD
GATE
where
I
GATE
is the GATE pin current, I
or I
, C
LOAD
is the load capacitance, and
C
GATE
is the total GATE capacitance (C
MOSFET and any external capacitance connected from
the GATE output pin to the GATE reference – GND or
source).
For the 3.3V outputs and 12V outputs (if no external 12VGATE
output capacitors are implemented), the following equation
is used to determine the output slew rate.
I
OUT
LOAD 3V 12V
GATE(3VCHARGE)
GATE(12VSINK)
ISS
of the external
dV
dt
C
LIM 3V 12V
Consequently, the overcurrent timer delay must be pro-
grammed to exceed the time it will take to charge the output
load to the input rail voltage level.
MAIN Outputs (Start-up Delay and Slew-Rate Control)
The 3.3V outputs act as source followers. In this mode of
operation,V
SOURCE
= [V
GATE
– V
] until the associated
output reaches 3.3V. The voltage on the gate of the MOSFET
will then continue to rise until it reaches 12V, which ensures
minimum R
. Note that a delay exists between the ON
command to a slot and the appearance of voltage at the slot’s
3.3V output. This delay is the time required to charge the
3VGATE output up to the threshold voltage of the external
MOSFET (typically about 3V).
TH(ON)
DS(ON)
t
C
V
I
3VDLY
GATE
GS(TH)
GATE(3VCHARGE)
the drain voltage in a time given by:
t
t
C
V
I
3V(SOURCE_DRAIN)
3VDLY
LOAD
DRAIN
LIM(3V)
integrator (by virtue of C
MILLER
, which is connected between
the MOSFET’s gate and drain). In this configuration, the
feedback action from drain to gate of the MOSFET causes
the voltage at the drain of the MOSFET to slew in a linear
fashion at a rate which satisfies the following equation:
dv / dt(12V)
I
C
GATE
MILLER
appearance of voltage at the slot’s 12V output. For a slot’s
12V output, that delay is given by the time required for the
capacitor from the gate of the MOSFET to its source (typically
five times the value of C
MILLER
) to charge to the threshold
voltage of the MOSFET (typically about 3V). In this instance,
the delay before the output voltage starts ramping can be
approximated by:
t
C
V
I
VDLY
GATE(TOTAL)
GS(TH)
GATE
12
is the sum of the C
GS
of the external
MOSFET, any external capacitance from the GATE output of
the MIC2592B to the source of the MOSFET, and C
MILLER
(external, if used).
Table 1 approximates the output slew-rate for various values
of C
GATE
when start-up is dominated by GATE capacitance
(external C
GATE
from GATE pin to ground plus C
GS
of the ex-
ternal MOSFET for the 3.3V rail; C
MILLER
for the 12V rail).
| I
GATE
| = 25μA
C
GATE
or C
MILLER
0.01μF*
GATE(TOTAL)
2.5V/ms
0.022μF*
1.136V/ms
0.047μF
0.532 V/ms
0.1μF
0.250V/ms
*
Values in this range will be affected by the internal parasitic capaci-
tances of the MOSFETs used, and should be verified experimentally.
Table 1. 3.3V and 12V Output Slew-Rate Selection for
Gate Capacitance Dominated Start-up
Power-Down Cycle
When one or more PCI slots are disabled via the MIC2592B
output control pins, ON[A/B] or AUXEN[A/B], the output volt-
age for each supply will discharge as a function of the RC
time constant produced by the controller’s internal resistance
(R
DIS
) connected to the output and the load capacitance
(C
LOAD
). The typical value of R
DIS
for each supply is listed
in the Electrical Characteristics Table. The charts below in
Figure 7 display curves of the fall time (90% - 10%) as a
function of the output load capacitance for both the 3V and
12V MAIN outputs.
0
200
400
600
800
1000
1200
0
5
0
100
150
200
250
L
FALL TIME (ms)
3V Output Discharge as a
Function of Load Capacitance
0
200
400
600
800
1000
1200
0
500
1000 1500 2000 2500
FALL TIME (ms)
L
12V Output Discharge as a
Function of Load Capacitance
Figure 7. 3V and 12V Output Discharge vs. Load
Capacitance
Standby Mode
Standby mode is entered when one or more of the MAIN
supply inputs (12VIN and/or 3VIN) is below its respective
UVLO threshold or OFF. The MIC2592B also supplies
3.3V auxiliary outputs (VAUX[A/B]), satisfying PCI Express
specifications. These outputs are fed via the VSTBY[A/B]
input pins and controlled by the AUXEN[A/B] input pins
or via their respective bits in the Control Registers. These
dv/dt (load)
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