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參數(shù)資料
| 型號(hào)： | MIC2592B-3YTQ |
| 廠商： | MICREL INC |
| 元件分類： | 電源管理 |
| 英文描述： | Dual-Slot PCI Express Hot-Plug Controller |
| 中文描述： | 1-CHANNEL POWER SUPPLY SUPPORT CKT, PQFP48 |
| 封裝： | LEAD FREE, TQFP-48 |
| 文件頁數(shù)： | 16/31頁 |
| 文件大?。?/td> | 1916K |
| 代理商： | MIC2592B-3YTQ |
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MIC2592B
Functional Description
Hot Swap Insertion
When circuit boards are inserted into systems carrying live
supply voltages (“hot-plugged”), high inrush currents often
result due to the charging of bulk capacitance that resides
across the circuit board’s supply pins. This transient inrush
current can cause the system’s supply voltages to temporarily
go out of regulation, causing data loss or system lock-up. In
more extreme cases, the transients occurring during a hot-
plug event may cause permanent damage to connectors or
on-board components.
The MIC2592B addresses these issues by limiting the in-
rush currents to the load (PCI Express Board), and thereby
controlling the rate at which the load’s circuits turn-on. In
addition to this inrush current control, the MIC2592B offers
input and output voltage supervisory functions and current
limiting to provide robust protection for both the system and
circuit board.
System Interface
The MIC2592B employs two system interfaces: the hard-
ware Hot-Plug Interface (HPI) and the System Management
Interface (SMI). The HPI includes ON[A/B], AUXEN[A/B],
as well as /FAULT[A/B]; the SMI consists of SDA, SCL,
and /INT, whose signals conform to the levels and timing of
the SMBus specification. The MIC2592B can be operated
exclusively from the SMI, or can employ the HPl for power
control while continuing to use the SMI for access to all but
the power control registers.
In addition to the basic power control features of the MIC2592B
accessible by the HPI, the SMI also gives the host access to
the following information from the part:
Fault conditions occurring on each supply.
GPI_[A0/B0] pin status
When using the System Management Interface for power
control, do not use the Hot-Plug Interface. Conversely, when
using the Hot-Plug Interface for power control, do not execute
power control commands over the System Management
Interface bus (all other register accesses via the SMI bus
remain permissible while in the HPI control mode). When
utilizing the SMI exclusively, the HPI input pins (ON[A/B],
AUXEN[A/B], and /FORCE_ON[A/B]) should be configured
as shown below in Figure 6 (Disabling HPI when SMI control
is used). This configuration safeguards the power slots in the
event that the SMBus communication link is disconnected
for any reason.
Micrel
March 2005
16
M9999-033105
MIC2592B
A2
A1
/INT
SDA
SCL
A0
V
STBY
V
STBY
100k
47
48
37
39
40
41
100k
Disabling SMI when
HPI Control is used
Disabling HPI when
SMI Control is used
100k
/INT
/FORCE_ONB
AUXENA
AUXENB
ONA
ONB
100k
100k
/FORCE_ONA
MIC2592B
9
28
45
42
44
43
Figure 6. Input Pin Configuration for Disabling HPI/SMI Control
Additionally, when utilizing the HPI exclusively, the SMBus
(or SMI) will be inactive if the input pins (SDA, SCL, A0, A1,
and A2) are configured as shown in Figure 6 below (Disabling
SMI when HPI Control is used).
Power Stability and Power-On Reset
The MIC2592B utilizes VSTBY[A/B] as the main supply input
source. VSTBY[A/B] is required for proper operation of the
MIC2592B’s SMBus and registers and must be applied at
all times. To ensure that the MIC2592B controller operates
properly, the V
input must be stable and remain above
STBY
the undervoltage lockout (UVLO) threshold once applied.
Sufficient input bulk capacitance should be used to prevent
the supply from "drooping", causing VSTBY[A/B] to fall below
the UVLO threshold. Also, decoupling capacitors should be
placed at each of the MIC2592B inputs in order to filter high
frequency noise transients.
V
must be the first supply input applied followed by the
STBY
MAIN supply inputs of 12V
IN
and 3V
IN
. A Power-On Reset
(POR) cycle is initiated after VSTBY[A/B] rises above its
UVLO threshold and remains valid at that voltage for 250μs.
All internal registers are cleared after POR. If VSTBY[A/B] is
recycled, the MIC2592B enters a new power-on-reset cycle.
The SMBus is ready for access at the end of the POR cycle
(250μs after VSTBY[A/B] is valid). During t
POR
, all outputs
remain off. In most applications, the total POR interval will
consist of the time required to charge the V
input (by-
pass) capacitance to the UVLO threshold plus the internal
t
POR
. The following equation is used to approximate the total
POR interval:
STBY
t
POR_TOTAL(μS)
=
C
STBY(μF)
V
ULVO(STBY)
I
CHARGE(STBY)
(A)
t
POR
(μS)
10
6
where C
is the V
STBY
I
is the current supplied by the V
source
to charge the capacitance.
Power-Up Cycle
Enabling the GATE output
When a slot's MAIN supplies are off, the 12VGATE pin is held
high with an internal pull-up. Similarly, the 3VGATE pin is
internally held low. When the MAIN supplies of the MIC2592B
are enabled by asserting ON[A/B], the 3VGATE[A/B] and
12VGATE[A/B] pins are each connected to a constant cur-
rent supply. These supplies are each nominally 25μA. For a
slot’s 3VGATE pin, this is a current source; for the 12VGATE
pin, this is a current sink.
input bulk bypass capacitance and
STBY
STBY
CHARGE(STBY)
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