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參數資料
| 型號： | MIC1832N |
| 廠商： | MICREL INC |
| 元件分類： | 電源管理 |
| 英文描述： | RSO-S_D(Z) Series - Econoline Regulated DC-DC Converters; Input Voltage (Vdc): 05V; Output Voltage (Vdc): 3.3V; Power: 1W; 2:1 and 4:1 Wide Input Voltage Ranges; 1kVDC, 2kVD & 3kVDC Isolation; UL94V-0 Package Material; Continuous Short Circuit Protectionwith Current Foldback; Low Noise; No External Capacitor needed; Efficiency to 83% |
| 中文描述： | 1-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDIP8 |
| 封裝： | DIP-8 |
| 文件頁數： | 6/8頁 |
| 文件大小： | 164K |
| 代理商： | MIC1832N |
6
Power Monitor
The RST and RST pins are asserted whenever VCC
falls below the reset threshold voltage as determined by
the TOL pin. A 5% tolerance level (2.88V reset
threshold voltage) can be selected by connecting the
TOL pin to ground and a 10% tolerance (2.55V reset
threshold voltage) can be selected by connecting the
TOL pin to VCC. The reset pins will remain asserted for
a period of 250ms after VCChas risen above the reset
threshold voltage. The reset function ensures the
microprocessor is properly reset and powers up into a
known condition after a power failure. RST will remain
valid with VCCas low as 1.4V.
Watchdog Timer
The microprocessor can be monitored by connecting
the ST pin (watchdog input) to a bus line or I/O line. If a
high-to-low transition doesn’t occur on the ST pin within
the watchdog timeout period (determined by TD pin, see
Table 1), the RST and RST pins will be asserted
resulting in a microprocessor reset. RST and RST will
remain asserted for at least 250ms when this occurs. A
minimum pulse of 75ns or any transition high-to-low on
the ST pin will reset the watchdog timer. The watchdog
timer will be reset if ST sees a valid transition within the
watchdog timeout period.
Pushbutton Reset Input
The PBRST input can be driven with a manual
pushbutton switch or with external logic signals. The
input is internally debounced and requires an active low
signal to force the reset outputs into their active states.
The PBRST input will recognize any pulse that is 20ms
in duration or greater and will ignore all pulses that are
less than 1ms in duration.
Figure 1. Power-Up/Power-Down Sequence
Circuit Description
V
CC
RST
RST
t
RPU
V
CCTP
t
RPD
V
CCTP
Figure 3. Pushbutton Reset
Figure 2. Watchdog Input
RST
RST
t
RST
t
PDLY
PBRST
t
PB
t
TD
ST
t
ST
Note:
The maximum time between high-to-low transitions (t
TD
) on the
watchdog input (ST) is determined by the voltage applied to the
TD pin. If the watchdog input sees a high-to-low transition prior to
the timeout period, the watchdog timer will be reset.
MIC1832
μ
P Supervisory Circuit
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