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參數資料
| 型號： | MH8V7245BWZTJ-6 |
| 廠商： | Mitsubishi Electric Corporation |
| 元件分類： | 圓形連接器 |
| 英文描述： | Circular Connector; Body Material:Aluminum; Series:PT00; No. of Contacts:23; Connector Shell Size:16; Connecting Termination:Solder; Circular Shell Style:Wall Mount Receptacle; Circular Contact Gender:Socket |
| 中文描述： | 超頁模式603979776 -位（8388608 - Word的72 -位）動態(tài)隨機存儲器 |
| 文件頁數： | 8/23頁 |
| 文件大?。?/td> | 147K |
| 代理商： | MH8V7245BWZTJ-6 |
MITSUBISHI LSIs
MH8V7245BAZTJ -5, -6
Preliminary Spec.
Specifications subject to
change without notice.
MITSUBISHI
ELECTRIC
( / 23 )
8
9/Nov. /1998
HYPER PAGE MODE 603979776 - BIT ( 8388608 - WORD BY 72 - BIT ) DYNAMIC RAM
MIT-DS-0284-0.0
Hyper Page Mode Cycle (Read, Early Write, Read -Write, Read-Modify-Write Cycle,
Read Write Mix Cycle,Hi-Z control by /OE or /W) (Note 25)
Note 25: All previously specified timing requirements and switching characteristics are applicable to their respective Hyper page mode cycle.
26: tRAS(min) is specified as two cycles of /CAS input are performed.
27: tCP(max) is specified as a reference point only. If tCP
≥
tCP(max),access time is controlled exclusively by tCAC.
Limits
Parameter
Symbol
Min
20
55
10
Max
(Note26)
(Note27)
13
100000
/CAS before /RAS Refresh Cycle (Note 28)
Limits
Parameter
Symbol
Unit
Min
10
5
Max
Note 28: Eight or more /CAS before /RAS cycles instead of eight /RAS cycles are necessary for proper operation of /CAS before /RAS refresh
mode.
-5
-5
Min
25
66
10
Max
16
100000
-6
Min
10
5
Max
-6
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tHPC
tHPRWC
tDOH
tRAS
tCP
tCPRH
tCPWD
tCHOL
tOEPE
tWPE
tHCWD
tHAWD
tHPWD
tHCOD
tHAOD
tHPOD
Hyper page mode read/write cycle time
Hyper page mode read write/read modify write cycle time
Output hold time from /CAS low
/RAS low pulse width for read write cycle
/CAS high pulse width
/RAS hold time after /CAS precharge
Delay time, /CAS precharge to W low
Hold time to maintain the data Hi-Z until /CAS access
/OE Pulse width (Hi-Z control)
/W Pulse width (Hi-Z control)
Delay time, /CAS low to /W low after read
Delay time, Address to /W low after read
Delay time, /CAS precharge to /W low after read
Delay time, /CAS low to /OE high after read
Delay time, Address to /OE high after read
Delay time, /CAS precharge to /OE high after read
33
43
65
8
38
50
77
10
(Note24)
ns
ns
ns
ns
tCSR
tCHR
tRSR
tRHR
/CAS setup time before /RAS low
/CAS hold time after /RAS low
Read setup time before /RAS low
Read hold time after /RAS low
15
5
15
5
7
7
7
7
7
7
40
43
13
28
47
50
15
32
25
28
30
33
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