參數(shù)資料
型號: MH8D64AKQC-75
廠商: Mitsubishi Electric Corporation
元件分類: 圓形連接器
英文描述: Circular Connector; No. of Contacts:21; Series:MS27484; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:22; Circular Contact Gender:Socket; Circular Shell Style:Straight Plug; Insert Arrangement:22-21 RoHS Compliant: No
中文描述: 536870912位(8388608字,64位),雙數(shù)據(jù)速率同步DRAM模塊
文件頁數(shù): 1/40頁
文件大?。?/td> 340K
代理商: MH8D64AKQC-75
MH8D64AKQC-75,-10
536,870,912-BIT (8,388,608-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0419-0.1
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
1
DESCRIPTION
APPLICATION
Main memory unit for Note PC, Mobile etc.
FEATURES
Type name
133MHz
MH8D64AKQC-10
MH8D64AKQC-75
-
Utilizes industry standard 8M X 16 DDR Synchronous DRAMs
in TSOP package , industry standard EEPROM(SPD) in
TSSOP package
-
200pin SO-DIMM
-
Vdd=Vddq=2.5v±0.2V
- Double data rate architecture; two data transfers per
clock cycle
- Bidirectional, data strobe (DQS) is transmitted/received
with data
- Differential clock inputs (CLK and /CLK)
-
DLL aligns DQ and DQS transitions with CLK transition edges of DQS
- Commands entered on each positive CLK edge
- Data and data mask referenced to both edges of DQS
- 4bank operation concontrolled byBA0,BA1(Bank Address
,discrete)
- /CAS latency- 2.0/2.5 (programmable)
- Burst length- 2/4/8 (programmable)
- Burst Type - sequential/interleave(programmable)
- Auto precharge / All bank precharge controlled by A10
- 4096 refresh cycles /64ms
- Auto refresh and Self refresh
- Row address A0-11 / Column address A0-8
- SSTL_2 Interface
- Module 1bank Configration
Max.
Frequency
100MHz
The MH8D64AKQC is 8388608 - word x 64-bit Double
Data Rate(DDR) Synchronous DRAM mounted module.
This consists of 4 industry standard 8M x 16 DDR
Synchronous DRAMs in TSOP with SSTL_2 interface which
achieves very high speed data rate up to 133MHz.
This socket-type memory module is suitable for main
memory in computer systems and easy to interchange or
add modules.
CLK
Access Time
[component level]
+ 0.75ns
+ 0.8ns
(Front)
(Back)
1
2
199
200
PCB Outline
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