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參數(shù)資料
| 型號： | MH89770 |
| 廠商： | Mitel Networks Corporation |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 中文描述： | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| 文件頁數(shù)： | 12/36頁 |
| 文件大?。?/td> | 836K |
| 代理商： | MH89770 |
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MH89770
Preliminary Information
4-136
average output data rate, the channel count and bit
count in the phase status word will be seen to
decrease over time, indicating that the E8Ko rising
edge, and therefore the DS1 frame boundary is
moving with respect to the ST-BUS frame pulse.
Conversely, a lower average input data rate will
result in an increase in the phase reading.
In an application where it is necessary to minimize
jitter transfer from the received clock to the local
system clock, a phase lock loop with a relatively
large time constant can be implemented using
information provided by the phase status word. In
such a system, the local 2.048 MHz clock is derived
from a precision VCO. Frequency corrections are
made on the basis of the average trend observed in
the phase status word. For example, if the channel
count in the phase status word is seen to increase
over time, the feedback applied to the VCO is used
to decrease the system clock frequency until a
reversal in the trend is observed.
The elastic buffer in the MT8977 permits the device
to handle 26 ST-BUS channels or 156 UI of jitter/
wander (see description of elastic buffer in the next
section). In order to prevent slips from occurring, the
frequency corrections would have to be implemented
such that the deviation in the phase status word is
limited to 26 channels peak-to-peak. It is possible to
use a more sophisticated protocol, which would
center
the
elastic
buffer
jitter/wander to be handled. However, for most
applications, including ACCUNET
T1.5 (138 UI), the
156 UI of jitter/wander tolerance is acceptable.
and
permit
more
Received Signalling Bits
The A, B, C and D signalling bits are output from the
device in the 24 Per Channel Status Words. Their
location in the serial steam output at CSTo is shown
in Figure 3 and the bit positions are shown in Table
11. The internal debouncing of the signalling bits can
be turned on or off by Master Control Word 1. In ESF
mode, A, B, C and D bits are valid. Even though the
signalling bits are only received once every six
frames the device stores the information so that it is
available on the ST-BUS every frame. The ST-BUS
will always contain the most recent signalling bits.
The state of the signalling bits is frozen if
synchronization is lost.
In D3/D4 mode, only the A and B bits are valid. The
state of the signalling bits is frozen when terminal
frame synchronization is lost. The freeze is disabled
when
the
device
regains
synchronization. The signalling bits may go through
terminal
frame
a random transition stage until the device attains
multiframe synchronization.
Clock and Framing Signals
The MH89770 has a built in clock extraction circuit
which creates a 1.544 MHz clock synchronized to
the received DS1 signal. This clock is used internally
by the MH89770 to clock in data received on RxT
and RxR, and is also output at the E1.5o pin. The
circuit has been designed to operate within the
constraints imposed by the minimum 1’s density
requirements, typically specified for T1 networks
(maximum of 15 consecutive 0’s).
The extracted clock is internally divided by 193 and
aligned with the received DS1 frame. The resulting 8
kHz signal is output at the E8Ko pin and can be used
to phase lock the local system C2 and the transmit
C1.5 clocks to the extracted clock.
The MH89770 requires three clock signals which
have to be generated externally. The ST-BUS
interface on the device requires a 2.048 MHz signal
which is applied at the C2i pin and an 8 kHz
framing signal applied at the F0i pin. The framing
signal is used to delimit individual ST-BUS frames.
Figure 19 illustrates the relationship between the C2i
and F0i signals. The F0i signal can be derived from
the 2.048 MHz C2 clock. The transmit side of the
DS1 interface requires a 1.544 MHz clock applied at
C1.5i. The C1.5 and C2 clocks must be phase
locked. There must be 193 clock cycles of the C1.5
clock for every 256 cycles of the C2 clock in order for
the 2.048 to 1.544 rate converter to function properly.
Figure 5 - MT8941 Clock Generator
F0i
C12i
MS1
C8Kb
C16i
MS0
MS2
MS3
F0b
C4b
C2o
ENC4o
ENC2o
CVb
ENCv
C1.5
+5V
F0i
C4i
C2i
+5V
Yo
5V
Ai
Bi
MT8941
DPLL #1
DPLL #2
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MH89770S | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89790B | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89790BN | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89790BS | Ultraframer DS3/E3/DS2/E2/DS1/E1/DS0 |
| MH89791 | CEPT PCM 30 Transmit Equalizer Advance Information |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH89770N | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/ESF Framer & Interface Preliminary Information |
| MH89770S | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:T1/ESF Framer & Interface Preliminary Information |
| MH89790B | 制造商:MITEL 功能描述: 制造商:ZARLNK 功能描述: |
| MH89790BN | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface Preliminary Information |
| MH89790BS | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ST-BUS⑩ FAMILY CEPT PCM 30/CRC-4 Framer & Interface Preliminary Information |
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