
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM
MH32S72AQJA-7, -8
17/Mar./2000
MIT-DS-0371-0.2
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
READ CYCLE (single bank)
BL=4,CL=3,Buffer mode(REGE="L")
REGE
23
/CS
/RAS
/CAS
/WE
CKE
BA0,1
DQ
X
X
X
0
Y
0
0
Q0
Q0
Q0
Q0
X
X
X
0
Y
0
Q0
Q0
ACT#0
READ#0
PRE#0
ACT#0
READ#0
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
tRCD
tRAS
tRP
tRC
tRCD
CL=3
READ to PRE
≥
BL allows full data out
DQM read latency =2
CLK
Italic parameter
indicates minimum case
A0-9
A10
DQM
A11