參數(shù)資料
型號(hào): MH32D64KQH-10
廠商: Mitsubishi Electric Corporation
英文描述: 2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
中文描述: 2147483648位(33554432字64位),雙數(shù)據(jù)速率同步DRAM模塊
文件頁(yè)數(shù): 35/40頁(yè)
文件大?。?/td> 350K
代理商: MH32D64KQH-10
MH32D64KQH-75,-10
2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0417-0.2
17.May.2001
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
35
[Power DOWN]
The purpose of CLK suspend is power down. CKE is synchronous input except during the self-refresh
mode. A command at cycle is ignored. From CKE=H to normal function, DLL recovery time is NOT
required in the condition of the stable CLK operation during the power down mode.
/CLK
CLK
Power Down by CKE
Command
PRE
CKE
Command
ACT
CKE
Standby Power
Down
Active Power
Down
NOP
NOP
DM Function(BL=8,CL=2)
Command
DQS
DQ
DM
Write
READ
D0
D1
[DM CONTROL]
DM is defined as the data mask for writes. During writes,DM masks input data word by word. DM to
write mask latency is 0.
D3
D4
D5
D6
D7
masked by DM=H
Don't Care
Q2
Q3
Q4
Q5
/CLK
CLK
Q0
Q1
Q6
Valid
NOP
NOP
Valid
tXPNR/
tXPRD
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參數(shù)描述
MH32D64KQH-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,147,483,648-BIT (33,554,432-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MH32D72AKLA-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH32D72AKLA-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH32D72AKLB-10 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module
MH32D72AKLB-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:2,415,919,104-BIT (33,554,432-WORD BY 72-BIT) Double Data Rate Synchronous DRAM Module