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參數(shù)資料
| 型號(hào)： | MH2S64CWXTJ-1539 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| 中文描述： | 134217728位（2097152字，64位）SynchronousDRAM |
| 文件頁(yè)數(shù)： | 25/45頁(yè) |
| 文件大小： | 691K |
| 代理商： | MH2S64CWXTJ-1539 |
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MH2S64CZTJ/CWZTJ-12,-15,-1539
134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM
MITSUBISHI LSIs
( 25
MITSUBISHI
ELECTRIC
Oct.28.1996
Preliminary Spec.
Some contents are subject to change without notice.
MIT-DS-0019-0.4
SELF REFRESH
Self-refresh mode is entered by issuing a REFS command (/CS=/RAS=/CAS=L,
/WE=H, CKE=L). Once the self-refresh is initiated, it is maintained as log as CKE is
kept low.During the self-refresh mode, CKE is asynchronous and the only enabled
input (but asynchronous), all other inputs including CK0 are disabled and ignored, and
power consumption due to synchronous inputs is saved. To exit the self-refresh,
supplying stable CK0 inputs, asserting DESEL or NOP command and then asserting
CKE(REFSX). After tRC from REFSX both banks are in the idle state and a new
command can be issued after tRC, but DESEL or NOP commands must be asserted
till then.
Self-Refresh
CK
/S
/RAS
/CAS
/WE
CKE
A0-10
BA
Self Refresh Entry
Self Refresh Exit
X
0
minimum tRC
for recovery
Stable CK
NOP
new command
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MH2S64CWZTJ-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CWZTJ-1539 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CZTJ-12 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
| MH2S64CZTJ-15 | 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:134217728-BIT (2097152-WORD BY 64-BIT)SynchronousDRAM |
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