參數(shù)資料
型號(hào)： MH1V36CAM-7
廠商： Mitsubishi Electric Corporation
英文描述： FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
中文描述： 快速頁面模式37748736位（1048576 - Word的36位）動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁數(shù)： 4/18頁
文件大?。?/td> 190K
代理商： MH1V36CAM-7
MITSUBISHI
ELECTRIC
( 4
FAST PAGE MODE 37748736-BIT ( 1048576-WORD BY 36-BIT ) DYNAMIC RAM
MH1V36CAM-6,-7
MITSUBISHI LSIs
Preliminary Spec.
Some of contents are subject to change without notice.
MIT-DS-0027-0.0
21 May 1996
SWITCHING CHARACTERISTICS
(Ta=0~70°C , Vcc=3.3V +/-0.3V, Vss=0V, unless otherwise noted , see notes 5,12,13)
Note 5: An initial pause of 500us is required after power-up followed by a minimum of eight initialization cycles (any combination of cycles
containing a RAS clock such as RAS-Only refresh).
Note the RAS may be cycled during the initial pause . And any 8 RAS or RAS/CAS cycles are required after prolonged periods
(greater than 16.4 ms) of RAS inactivity before proper device operation is achieved.
6: Measured with a load circuit equivalent to VOH=2.4V(IOH=-2mA)/VOL=0.4V(IOL=2mA) load 100pF.
The reference levels for measuring of output signal are 2.0V(VOH) and 0.8V(VOL).
7: Assumes that t
RCDD
≥
t
RCD(max)
and t
ASC
≥
t
ASC(max).
8: Assumes that t
RCD
≤
t
RCD(max)
and t
RAD
≤
t
RAD(max).
If t
RCD
or
t
RAD
is greater than the maximum recommended value shown in this table,
t
RAC
will increase by amount that t
RCD
exceeds the value shown.
9: Assumes that t
RAD
≥
t
RAD(max)
and t
ASC
≤
t
ASC(max).
10: Assumes that t
CP
≤
t
CP(max)
and t
ASC
≥
t
ASC(max).
11: t
OFF(max)
and
t
OEZ (max)
defines the time at which the output achieves the high impedance state (I
OUT
≤
I +/- 10uAI) and is not reference to
V
OH(min)
or
V
OL(max).
Limits
Parameter
Access time from CAS
Access time from RAS
Columu address access time
Access time from CAS precharge
Access time from OE
Symbol
t
CAC
t
RAC
t
AA
t
CPA
t
OEA
t
CLZ
t
OFF
t
OEZ
Unit
Min
Max
15
60
Min
Max
20
70
-6
-7
ns
ns
ns
ns
ns
ns
ns
ns
0
0
5
0
0
5
35
40
20
20
30
35
15
15
Output low impedance time from CAS low
Output disable time after CAS high
Output disable time after OE high
(Note 6,7)
(Note 6,8)
(Note 6,9)
(Note 6,10)
(Note 6)
(Note 6)
(Note 11)
(Note 11)
Limits
Parameter
Refresh cycle time
RAS high pulse width
Delay time, RAS low to CAS low
Delay time, CAS high to RAS low
Delay time, RAS high to CAS low
CAS high pulse width
Symbol
t
REF
t
RP
t
RCD
t
CRP
t
RPC
t
CPN
t
RAD
t
ASR
t
ASC
t
RAH
t
CAH
t
DZC
t
DZO
t
CDD
t
ODD
Unit
Min
Max
16.4
Min
Max
16.4
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
(Note19)
(Note14)
(Note15)
(Note16)
ns
50
35
10
50
45
30
0
40
20
10
10
50
10
15
0
0
10
15
1
0
50
20
10
10
15
0
0
10
15
1
t
T
Column address delay time from RAS low
Row address setup time before RAS low
Column address setup time before CAS low
Row address hold time after RAS low
Column address hold time after CAS low
Delay time, data to CAS low
Delay time, data to OE low
Delay time, CAS high to data
Delay time, OE high to data
Transition time
TIMING REQUIREMENTS (For Read, Write, Read-Modify-Write ,Refresh, and Fast-Page Mode Cycles)
(Ta=0 ~ 70 °C, Vcc=3.3V +/- 0.3V, Vss=0V, unless otherwise noted See notes 12,13)
Note 12: The timing requirements are assumed t
T
=5ns.
13: V
IH(min)
and V
IL(max)
are reference levels for measuring timing of input signals.
14: t
RCD(max)
is specified as a reference point only. If t
RCD
is less than t
RCD(max),
access time is t
RAC.
If t
RCD
is greater than t
RCD(max),
access
time is controlled exclusively by t
CAC
or t
AA.
t
RCD(min)
is specified as t
RCD(min)
=t
RAH(min)
+2t
H
+t
ASC(min).
15: t
RAD(max)
is specified as a reference point only. If t
RAD
≥
t
RAD(max)
and t
ASC
≤
t
ASC(max),
access time is controlled exclusively by t
AA.
16: t
ASC(max)
is specified as a reference point only. If t
RCD
≥
t
RCD(max)
and t
ASC
≥
t
ASC(max),
access time is controlled exclusively by t
CAC.
17:
Either t
DZC
or t
DZO
must be satisfied.
18: Either t
CDD
or t
ODD
must be satisfied.
19: t
T
is measured between V
IH(min)
and V
IL(max).
20
15
(Note17)
(Note17)
(Note18)
(Note18)
0
0
0
0
15
20
15
20
-6
-7
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