參數(shù)資料
型號(hào): MH16D64AKQC-10
廠商: Mitsubishi Electric Corporation
英文描述: JT 55C 55#20 PIN PLUG
中文描述: 1073741824位(16,777,216字64位),雙數(shù)據(jù)速率同步DRAM模塊
文件頁(yè)數(shù): 17/37頁(yè)
文件大?。?/td> 329K
代理商: MH16D64AKQC-10
MH16D64AKQC-75,-10
1,073,741,824-BIT (16,777,216-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
MIT-DS-0400-0.0
2.Nov.2000
Preliminary Spec.
Some contents are subject to change without notice.
MITSUBISHI LSIs
MITSUBISHI
ELECTRIC
17
AVERAGE SUPPLY CURRENT from Vdd
(Ta=0 ~ 70 , Vdd = VddQ = 2.5 ± 0.2V, Vss = VssQ = 0V, Output Open, unless otherwise noted)
C
AC OPERATING CONDITIONS AND CHARACTERISTICS
(Ta=0 ~ 70 C
TBD
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TBD
TBD
-10
-75
ACTIVE POWER-DOWN STANDBY CURRENT: One bank active;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
mA
mA
mA
SELF REFRESH CURRENT: CKE 0.2V
AUTO REFRESH CURRENT: t RC = t RFC (MIN)
OPERATING CURRENT: Burst = 2; Writes; Continuous burst; One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle
OPERATING CURRENT: Burst = 2; Reads; Continuous burst;One
bank active; Address and control inputs changing once per clock
cycle; CL = 2.5; t CK = t CK MIN; IOUT = 0 mA
ACTIVE STANDBY CURRENT: /CS > VIH (MIN); CKE > VIH (MIN);
One bank; Active-Precharge; t RC = t RAS MAX; t CK = t CK MIN;
DQ,DM and DQS inputs changing twice per clock cycle; address and
other control inputs changing once per clock cycle
IDLE STANDBY CURRENT: /CS > VIH (MIN); All banks idle;
CKE > VIH (MIN); t CK = t CK MIN; Address and other control inputs
changing once per clock cycle
IDD2P
PRECHARGE POWER-DOWN STANDBY CURRENT: All banks idle;
power-down mode; CKE VIL (MAX); t CK = t CK MIN
mA
OPERATING CURRENT: One Bank; Active-Read-Precharge;
Burst = 2; t RC = t RC MIN; CL = 2.5; t CK = t CK MIN; IOUT= 0
mA;Address and control inputs changing once per clock cycle
OPERATING CURRENT: One Bank; Active-Precharge;
t RC = t RC MIN; t CK = t CK MIN; DQ, DM and DQS inputs changing
twice per clock cycle; address and control inputs changing once per
clock cycle
Parameter/Test Conditions
IDD4R
IDD3N
mA
mA
mA
mA
mA
mA
IDD6
IDD5
IDD4W
IDD3P
IDD2N
IDD1
IDD0
Notes
Unit
Limits(max)
Symbol
Symbol
Parameter/Test Conditions
Limits
Min.
Max.
Unit
VIH(AC)
VIL(AC)
VID(AC)
VIX(AC)
High-Level Input Voltage (AC)
Low-Level Input Voltage (AC)
Input Differential Voltage, CLK and /CLK
Input Crossing Point Voltage, CLK and /CLK
Vref + 0.35
Vref - 0.35
V
V
V
V
μA
0.7
0.5*Vdd-0.2
Vdd + 0.6
IOZ
I
i
Off-state Output Current /Q floating Vo=0~V
DD
Q
Input Current / VIN=0 ~ VddQ
μA
-10
-16
10
16
0.5*Vdd+0.2
Notes
7
8
9
O
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MH16D64AKQC-75 制造商:MITSUBISHI 制造商全稱:Mitsubishi Electric Semiconductor 功能描述:1,073,741,824-BIT (16,777,216-WORD BY 64-BIT) Double Data Rate Synchronous DRAM Module
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