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參數(shù)資料
| 型號(hào)： | MGP3006X6 |
| 廠商： | SIEMENS A G |
| 元件分類： | XO, clock |
| 英文描述： | GHz PLL with I2C Bus and Four Chip Addresses |
| 中文描述： | PHASE LOCKED LOOP, 1300 MHz, PDSO16 |
| 封裝： | PLASTIC, DSO-16 |
| 文件頁(yè)數(shù)： | 1/21頁(yè) |
| 文件大?。?/td> | 450K |
| 代理商： | MGP3006X6 |
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Combined with a VCO (tuner), the
MGP 3006X
device, with four hard-switched chip
addresses, forms a digitally programmable phase-locked loop for use in television sets
with PLL-frequency synthesis tuning. The PLL permits precise crystal-controlled setting
of the frequency of the tuner oscillator between 16 and 1300 MHz in increments of
62.5 kHz, and, with a 2.4-GHz prescaler 1/2, in the TV-SAT band in increments of
125 kHz. The tuning process is controlled by a microprocessor via an
I
2
C Bus. The
I
2
C Bus noise immunity has been improved by a factor of 10 compared to the
SDA 3202-2, and the new crystal oscillator generates a sinusoidal signal, suppressing
the higher-order harmonics, which reduces the moiré noise considerably.
Type
Ordering Code
Package
MGP 3006X
Q67000-H5114
P-DSO-14-1 (SMD)
MGP 3006X
Q67006-H5114
P-DSO-14-1 Tape & Reel (SMD)
GHz PLL with
I
2
C Bus
and Four Chip Addresses
Bipolar IC
MGP 3006X
P-DSO-14-1
Features
G
1-chip system for MPU-control (
I
2
C Bus)
G
4 programmable chip addresses
G
Short pull-in time for quick channel switch-over
and optimized loop stability
G
2 high-current band switch outputs (20 mA)
G
Software-compatible with SDA 3202 series
G
Oxis III technology
Semiconductor Group
1
04.93
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