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參數(shù)資料
| 型號(hào)： | MF600SWI |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | Mirco Filter For ADSL CPE Side |
| 中文描述： | Mirco過(guò)濾器對(duì)于ADSL終端側(cè) |
| 文件頁(yè)數(shù)： | 8/11頁(yè) |
| 文件大?。?/td> | 119K |
| 代理商： | MF600SWI |
Product Specification
MF600SWI
Data sheet subject to change without notice
RDPS-MF051(R1)10/01/2002
SHEET 8 OF 11
5.4. DC characteristics :
All requirements of this specification can be met in the presence of all POTS loop currents
from 0 mA to 100 mA. This Single In-Line filter can pass POTS tip-to-ring DC voltages of 0
V to 105 V and ringing signals of 40 Vrms to 150 Vrms at any frequencies from 15.3 Hz to
68 Hz superimposed on DC voltages in the range from 0 V to 105 V. The DC resistance
from tip-to-ring at the line port interface with the phone interface shorted, shall be less than
or equal to 50 ohms for one filter. The DC resistance from tip-to-ground and from ring-to-
ground at the Phone interface with the Line interface open shall be greater than or equal to
10 Megohms. The ground point shall be local building or green wire ground. As an objective,
the DC resistance should exceed 10 M
.
5.5. Test methods :
5.5.1. Off-hook insertion loss :
The insertion loss of a device connected into a given transmission system is defined as
the ratio, expressed in dB, of the load power available ( before and after insertion )
delivered to the output network beyond the point of insertion at a given frequency. In
general, the insertion loss is defined as the ratio, expressed in dB of the power delivered
to a load with the circuit in place and the power delivered to a load without the circuit in
place. The added insertion loss shall be measured using the test up in figure 2. For
measuring POTS band insertion loss for single filter module also for single filter with four
added parallel load filters. General Insertion loss equation can be expressed as follows.
Insertion loss = 20 log
V2 / V1
dB where
V1 = the measured voltage value of load without LPF in circuit.
V2 = the measured voltage value of load with LPF in circuit.
The test setup is shown in drawing below.
Figure 2.
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