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參數(shù)資料
| 型號： | MF365A-LZCATXX |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 8/16-bit Data Bus Static RAM Card |
| 中文描述： | 16位產(chǎn)品數(shù)據(jù)總線靜態(tài)存儲器卡 |
| 文件頁數(shù)： | 9/11頁 |
| 文件大?。?/td> | 254K |
| 代理商： | MF365A-LZCATXX |
MITSUBISHI MEMORY CARD
STATIC RAM CARDS
MITSUBISHI
ELECTRIC
9/11
TIMING DIAGRAM (Attribute)
Read Cycle
An
V
IL
WE#=“H” level
REG#=“L” level
Note 6 : Test Conditions
Input pulse levels : V
I L
=0.4V, V
IH
=4.0V
Input pulse rise, fall time : tr=tf=10ns
Reference voltage
Input :
Output : V
OL
=0.8V, V
OH
=3.0V
V
I L
=0.8V, V
IH
=3.5V
(ten and tdis are measured when output voltage is± 500mV from steady state. )
100pF+1 TTL gate
5pF+1 TTL gate (at ten and tdis measuring)
7 : Writing is executed in overlap of CE# and WE# are “L” level. (only for Common Memory)
8 : Don’t apply inverted phase signal externally when Dm pin is in output mode.
9 : CE# is indicated as follows:
Read A/Write A : CE#=CE1#=CE2#
Read B/Write B : CE#=CE1#, CE2#=“H” level
Read C/Write C : CE#=CE2#, CE1#=“H” level
Load :
t
CR
R
t
a
(A)
R
ta
(CE)
R
ten
(CE)
R
ten
(OE)
R
tdis
(OE)
R
t
V(A)
R
ta
(OE)
R
OUTPUT VALID
Hi-Z
t
dis(CE)
R
V
IH
Dm
(D
OUT
)
V
OH
V
OL
OE#
V
IH
V
IL
CE#
V
IH
V
IL
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