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參數(shù)資料
| 型號(hào)： | MF3257-J8CATXX |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | 8/16-bit Data Bus Static RAM Card |
| 中文描述： | 16位產(chǎn)品數(shù)據(jù)總線靜態(tài)存儲(chǔ)器卡 |
| 文件頁數(shù)： | 12/16頁 |
| 文件大?。?/td> | 119K |
| 代理商： | MF3257-J8CATXX |
MITSUBISHI MEMORY CARD
STATIC RAM CARDS
MITSUBISHI
ELECTRIC
12/16 Apr. 1999 Rev. 1.2
PAGE MODE WRITE TIMING CHART
REG#=“L” level
Note 6 : Test Conditions
Input pulse levels : V
IL
=0.4V, V
IH
=2.8V
Input pulse rise, fall time : tr=tf=10ns
Reference voltage
Input : V
IL
=0.8V, V
IH
=2.4V
Output : V
OL
=0.8V, V
OH
=2.0V
(ten and tdis are measured when output voltage is ± 500mV from steady state. )
Load : 100pF + 1 TTL gate
5pF + 1 TTL gate (at ten and tdis measuring)
7 : Indicates the don’t care input
8 : Writing is executed in overlap of CE# and WE# are “L” level. (only for Common Memory)
9 : Don’t apply inverted phase signal externally when Dm pin is in output mode.
10 : CE# is indicated as follows:
Read A/Write A : CE#=CE1#=CE2#
Read B/Write B : CE#=CE1#, CE2#=“H” level
Read C/Write C : CE#=CE2#, CE1#=“H” level
tdis
(
OE
)
R
Hi-Z
An=(n>5)
An
(A
0
~A
5
)
CE#
OE#
WE#
D
IN
tw
(
WE
)
R
t
DL
R
tsu
(
OE-WE
)
R
tsu
(
A
)
R
t
BLC
R
th
(
CE
)
R
trec
(
WE
)
R
tsu
(
CE
)
R
t
(
D-WEH
)
R
th
(
D
)
R
0h
2h
4h
3Ch
3Eh
D
OUT
Hi-Z
th
(
OE-WE
)
R
tc
WR
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