參數(shù)資料
型號： MF280C51T-20R
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQFP44
封裝： QFP-44
文件頁數(shù)： 150/170頁
文件大小： 4133K
代理商： MF280C51T-20R
80
ATtiny4/5/9/10 [DATASHEET]
8127F–AVR–02/2013
12. Analog Comparator
The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the volt-
age on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator output,
ACO, is set. The comparator can trigger a separate interrupt, exclusive to the Analog Comparator. The user can
select Interrupt triggering on comparator output rise, fall or toggle. A block diagram of the comparator and its sur-
rounding logic is shown in Figure 12-1.
Figure 12-1. Analog Comparator Block Diagram.
See Figure 1-1 on page 2 for pin use of analog comparator, and Table 10-4 on page 49 and Table 10-5 on page 50
for alternate pin usage.
12.1
Register Description
12.1.1
ACSR – Analog Comparator Control and Status Register
Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the analog comparator is switched off. This bit can be set at any time
to turn off the analog comparator, thus reducing power consumption in Active and Idle mode. When changing the
ACD bit, the analog comparator Interrupt must be disabled by clearing the ACIE bit in ACSR. Otherwise an inter-
rupt can occur when the bit is changed.
Bits 6 – Res: Reserved Bit
This bit is reserved and will always read zero.
Bit 5 – ACO: Analog Comparator Output
Enables output of analog comparator. The output of the analog comparator is synchronized and then directly con-
nected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
Bit
765
4321
0
ACD
–
ACO
ACI
ACIE
ACIC
ACIS1
ACIS0
ACSR
Read/Write
R/W
R
R/W
Initial Value
000
0000
0
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