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參數(shù)資料
| 型號(hào)： | MF280C51-12R |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, PQFP44 |
| 文件頁(yè)數(shù)： | 27/290頁(yè) |
| 文件大?。?/td> | 4178K |
| 代理商： | MF280C51-12R |
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ARM9E-S Coprocessor Interface
6-6
Copyright 2000 ARM Limited. All rights reserved.
ARM DDI 0165B
If a coprocessor instruction busy-waits, PASS is asserted on every cycle until the
coprocessor instruction is executed. If an interrupt occurs during busy-waiting, PASS is
driven LOW, and the coprocessor stops execution of the coprocessor instruction.
A further output, LATECANCEL, cancels a coprocessor instruction when the
instruction preceding it caused a Data Abort, or a previous instruction caused a
watchpoint. LATECANCEL can be asserted even if there is no coprocessor instruction
being executed. For coprocessor instructions, LATECANCEL is valid on the rising
edge of CLK on the cycle that follows the first Execute cycle of the coprocessor
instruction. See CDP on page 6-14 for an example of LATECANCEL behavior.
On the rising edge of the clock, the ARM9E-S processor core examines the coprocessor
handshake signals CHSD[1:0] or CHSE[1:0]:
If a new instruction is entering the Execute stage in the next cycle, the core
examines CHSD[1:0].
If the currently executing coprocessor instruction requires another Execute cycle,
the core examines CHSE[1:0].
The handshake signals encode one of four states:
ABSENT
If there is no coprocessor attached that can execute the coprocessor
instruction, the handshake signals indicate the ABSENT state. In this
case, the ARM9E-S processor core takes the undefined instruction trap.
WAIT
If there is a coprocessor attached that can handle the instruction, but not
immediately, the coprocessor handshake signals are driven to indicate
that the ARM9E-S processor core must stall until the coprocessor can
catch up. This is known as the busy-wait condition. In this case, the
ARM9E-S processor core loops in an idle state waiting for CHSE[1:0]
to be driven to another state, or for an interrupt to occur.
If CHSE[1:0] changes to ABSENT, the undefined instruction trap is
taken. If CHSE[1:0] changes to GO or LAST, the instruction proceeds as
follows.
If an interrupt occurs, the ARM9E-S processor core is forced out of the
busy-wait state. This is indicated to the coprocessor by the PASS signal
going LOW. The instruction is restarted later and so the coprocessor must
not commit to the instruction (it must not change any of the coprocessor
state) until it has seen PASS HIGH, when the handshake signals indicate
the GO or LAST condition.
GO
The GO state indicates that the coprocessor can execute the instruction
immediately, and that it requires another cycle of execution. Both the
ARM9E-S processor core and the coprocessor must also consider the
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