參數(shù)資料
型號: MF0128M-07BTxx
廠商: Mitsubishi Electric Corporation
英文描述: 8/16-bit Data Bus Flash ATA PC Card
中文描述: 16位產(chǎn)品數(shù)據(jù)總線閃存阿拉木圖PC卡
文件頁數(shù): 26/32頁
文件大?。?/td> 211K
代理商: MF0128M-07BTXX
MITSUBISHI STORAGE CARD
Preliminary
ATA PC CARDS
MITSUBISHI
ELECTRIC
26
Oct.1999 Rev. 0.2
I/O READ (INPUT) TIMING
Limit
Symbol
Parameter
Min
Max
100
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
td(IORD)
th(IORD)
tw(IORD)
tsuA(IORD)
thA(IORD)
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
tdfINPACK(IORD)
tdrINPACK(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
The maximum load on
INPACK# and IOIS16#
are 1 LSTTL with 50 pF total load.
Data Delay after
IORD#
Data Hold following
IORD#
IORD#
Width Time
Address Setup before
IORD#
Address Hold following
IORD#
CE#
Setup before
IORD#
CE#
Hold following
IORD#
REG#
Setup before
IORD#
REG#
Hold following
IORD#
INPACK#
Delay Falling from
IORD#
INPACK#
Delay Rising from
IORD#
IOIS16#
Delay Falling from Address
IOIS16#
Delay Rising from Address
0
165
70
20
5
20
5
0
0
45
45
35
35
I/O WRITE (OUTPUT) TIMING
Limit
Symbol
Parameter
Min
60
30
165
70
20
5
20
5
0
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
tsu(IOWR)
th(IOWR)
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
Data Setup before
IOWR#
Data Hold following
IOWR#
IOWR#
Width Time
Address Setup before
IOWR#
Address Hold following
IOWR#
CE#
Setup before
IOWR#
CE#
Hold following
IOWR#
REG#
Setup before
IOWR#
REG#
Hold following
IOWR#
IOIS16#
Delay Falling from Address
IOIS16#
Delay Rising from Address
The maximum load on
INPACK#
and
IOIS16#
are 1 LSTTL with 50 pF total load.
35
35
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