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參數(shù)資料
| 型號： | MF0075M-03ATxx |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | null8/16-bit Data Bus Flash ATA PC Card |
| 中文描述： | null8/16-bit數(shù)據(jù)總線閃存阿拉木圖PC卡 |
| 文件頁數(shù)： | 15/29頁 |
| 文件大小： | 841K |
| 代理商： | MF0075M-03ATXX |
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MITSUBISHI STORAGE CARD
ATA PC CARDS
MITSUBISHI
ELECTRIC
15
1997.Nov. Rev. 1.2
ATA Register Specifications
Data Register
This register is a 16 bit register which is used to transfer
data blocks between the card data buffer and the host.
Data may be transferred by either a series of word
accesses to the Data register or a series of byte accesses
to the Data register.
D15
D14
D13
D12
Data Word
Odd Data Byte
D11
D10
D9
D8
D7
D6
D5
D4
Data Word
Data Byte
D3
D2
D1
D0
Error Register
This register contains additional information about the
source of an error which has occurred in processing of the
preceding command. This register should be checked by
the host when ERR bit in the Status register is set. The
Error register is a read only register.
D7
BBK
D6
UNC
D5
0
D4
IDNF
D3
0
D2
D1
0
D0
ABRT
AMNF
Field
BBK
function
This bit is set when a Bad Block is detected in requested ID
field. Host can not read/write on data area that is marked as
a Bad Block.
This bit is set when Uncorrectable error is occurred at
reading the card.
The requested sector ID is in error or cannot be found.
This bit is set if the command has been aborted because of
the card status condition. (Not ready, Write fault, etc.) or
when an invalid command has been issued.
This bit is set in case of a general error.
UNC
IDNF
ABRT
AMNF
Feature Register
This register is written by the host to provide command
specific information to the drive regarding features of the
drive which the host wish to utilize. The Feature register is
a write only register.
D7
D6
D5
D4
Feature byte
D3
D2
D1
D0
Sector Count Register
This register is written by the host with the number of
sectors or blocks to be processed in the subsequent
command. After the command is complete, the host may
read this register to obtain the count of sectors left
unprocessed by the command.
D7
D6
D5
D4
Sector Count
D3
D2
D1
D0
Sector Number Register
This register is written by the host with the starting sector
number to be used in the subsequent Cylinder-Head-
Sector command. After the command is complete, the
host may read the final sector number from this register.
When logical block addressing is used, this register is
written by the host with bit7 to 0 of the starting logical
block number and contains bit7 to 0 of the final logical
block number after the command is complete.
D7
D6
D5
D4
Sector Number
D3
D2
D1
D0
Logical Block Number bits A07-A00(LBA Addressing)
Cylinder Low Register
This register is written by the host with the low-order byte
of the starting cylinder address to be used in the
subsequent Cylinder-Head-Sector command. After the
command is complete, the host may read the low-order
byte of the final cylinder number from this register. When
logical block addressing is used, this register is written by
the host with bits15 to 8 of the starting logical block
number and contains bits15 to 8 of the final logical block
number after the command complete.
D7
D6
D5
D4
D3
D2
D1
D0
Cylinder Low Byte
Logical Block Number bits A15-A08(LBA Addressing)
Cylinder High Register
This register is written by the host with the high-order byte
of the starting cylinder address to be used in the
subsequent Cylinder-Head-Sector command. After the
command is complete, the host may read the high-order
byte of the final cylinder number from this register. When
logical block addressing is used, this register is written by
the host with bits 23 to 16 of the starting logical block
number and contains bits23 to 16 of the final logical block
number after the command is complete.
D7
D6
D5
D4
D3
D2
D1
D0
Cylinder High Byte
Logical Block Number bits A23-A16(LBA Addressing)
Drive/Head Register
The Drive/Head register is used to specify the selected
drive of a pair of drives sharing a set of registers.
D7
X
D6
LBA
D5
X
D4
DRV
D3
HS3
LBA27
D2
HS2
LBA26
D1
HS1
LBA25
D0
HS0
LBA24
Field
X
LBA
function
Undefined . “0” or “1”.
This bit is “0” for CHS addressing and “1” for Logical
Block addressing.
This bit is number of the drive which the host has
selected. When DRV is cleared, Drive0 is selected.
When DRV is set, Drive1 is selected. The card is
selected to be Drive0 or to be Drive1 using the “Copy”
field of the PC Card Socket Copy Register.
DRV
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| MF00L1NCGD | 功能描述:旋鈕開關(guān) Rotary RoHS:否 制造商:C&K Components 位置數(shù)量:5 卡片組數(shù)量: 每卡片組極數(shù):2 電流額定值:250 mA 電壓額定值:125 V 指數(shù)角: 觸點類型: 觸點形式:DPST 端接類型:Solder 安裝類型:Panel 觸點電鍍:Silver |
| MF00L1NCGF | 功能描述:旋鈕開關(guān) Rotary RoHS:否 制造商:C&K Components 位置數(shù)量:5 卡片組數(shù)量: 每卡片組極數(shù):2 電流額定值:250 mA 電壓額定值:125 V 指數(shù)角: 觸點類型: 觸點形式:DPST 端接類型:Solder 安裝類型:Panel 觸點電鍍:Silver |
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