參數(shù)資料
型號： MF0064M-04BAXX
廠商： Mitsubishi Electric Corporation
英文描述： 8/16-bit Data Bus CompactFlash Card
中文描述： 16位產(chǎn)品數(shù)據(jù)總線CF卡
文件頁數(shù)： 4/31頁
文件大?。?/td> 217K
代理商： MF0064M-04BAXX
MITSUBISHI STORAGE CARD
MF0XXXX-04BAXX series
CompactFlash CARDS
Jun.2000
. Rev. 1.1
MITSUBISHI
ELECTRIC
4/31
Signal Description(Continued)
Signal Name
Attribute Memory Select[REG#]
(PC Card Memory Mode)
Attribute Memory Select[REG#]
(PC Card I/O Mode)
Attribute Memory Select[REG#]
(True IDE Interface)
Battery Voltage Detect[BVD2]
(PC Card Memory Mode)
Audio Digital Waveform[SPKR#]
(PC Card I/O Mode)
DASP#
(True IDE Interface)
Card Reset[RESET]
(PC Card Memory Mode)
Card Reset[RESET]
(PC Card I/O Mode)
Card Reset[RESET#]
(True IDE Interface)
Wait[WAIT#]
(PC card Memory Mode)
Wait[WAIT#]
(PC card I/O Mode)
IORDY
(True IDE Interface)
Input Port Acknowledge[INPACK#]
(PC Card I/O Mode)
I/O
I
Pin No.
Description
44
When this signal is asserted, access is limited to
Attribute Memory with OE#/WE# and I/O Space
with IORD#/IOWR#.
This input signal is not used for this mode and
should be connected to Vcc by the host.
This output is driven to a high-level.
O
45
SPKR# is kept negated because this Card does not
have digital audio output.
This signal is the DISK Active/Slave Present signal
in the Master/Slave handshake protocol.
By assertion of this signal, all registers of this Card
are cleared. This signal should be kept to High-Z by
the host for at least 1ms after Vcc applied.
I/O
I
41
This input pin is the active low hardware reset from
the host.
This signal is asserted to delay completion of the
memory or I/O access cycle.
O
42
O
43
This signal is asserted when the Card is selected
and can respond to an I/O Read cycle at the
address on the address bus.
This signal is not used for this mode and should not
be connected at the host.
This output is driven to a high-level.
Input Port Acknowledge[INPACK#]
(True IDE Interface)
Battery Voltage Detect[BVD1]
(PC Card Memory Mode)
STSCHG#
(PC Card I/O Mode)
O
46
This signal is asserted low to alert the host to
changes in the status of Configuration Status
Register in the Attribute Memory Space.
This signal is the Pass Diagnostic signal in the
Master/Slave handshake protocol.
VS1 is grounded so that the Card CIS can be read
at 3.3V and VS2 is N.C.
This signal is not used for this mode.
PDIAG#
(True IDE Interface)
Voltage Sense[VS1, VS2]
I/O
O
33, 40
Cable Select[CSEL]
(PC Card Memory Mode)
Cable Select[CSEL]
(PC Card I/O Mode)
Cable Select[CSEL]
(True IDE Interface)
-
39
-
I
This signal is used to configure this Card as a
Master or a Slave. When this signal is grounded,
this Card is configured as a Master. When this
signal is Open, this Card is configured as a Slave.
5V or 3.3V power.
Ground.
Vcc
GND
-
-
13, 38
1, 50
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