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參數資料
| 型號： | MD80C52XXX-12 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 12 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁數： | 7/14頁 |
| 文件大小： | 1018K |
| 代理商： | MD80C52XXX-12 |
2
8393BS-MCU Wireless-02/13
ATmega256/128/64RFR2
1 Pin Configurations
Figure 1-1. Pinout ATmega256/128/64RFR2
Note:
The large center pad underneath the QFN/MLF package is made of metal and internally connected
to AVSS. It should be soldered or glued to the board to ensure good mechanical stability. If the
center pad is left unconnected, the package might loosen from the board. It is not recommended to
use the exposed paddle as a replacement of the regular AVSS pins.
2 Disclaimer
Typical values contained in this datasheet are based on simulation and characterization
results of other AVR microcontrollers and radio transceivers manufactured in a similar
process technology. Minimum and Maximum values will be available after the device is
characterized.
1
[PF3:ADC3:DIG4]
[PF2:ADC2:DIG2]
2
3
[PF5:ADC5:TMS]
[PF4:ADC4:TCK]
4
5
[PF7:ADC7:TDI]
[PF6:ADC6:TDO]
6
7
[RFP]
[AVSS_RFP]
8
9
[AVSS_RFN]
[RFN]
10
11
[RSTN]
[TST]
12
13
14
[RSTON]
[PG0:DIG3]
56 55 54 53 52 51
62 61 60 59 58 57
64 63
ATmega256/128/64RFR2
Exposed paddle: [AVSS]
[DVSS]
[PE0:RXD0:PCINT8]
[PE1:TXD0]
[PE2:XCK0:AIN0]
[CLKI]
[DEVDD]
[DVSS]
[PB0:SSN:PCINT0]
[PB1:SCK:PCINT1]
[PB2:MOSI:PDI:PCINT2]
[PB3:MISO:PDO:PCINT3]
[PB4:OC2A:PCINT4]
[PB5:OC1A:PCINT5]
[PB6:OC1B:PCINT6]
31 32
17 18 19 20 21
23
22
24 25 26 27
0
28
[P
D
3
:T
X
D
1
:I
N
T
3
]
[P
D
2
:R
X
D
1
:I
N
T
2
]
[P
D
1
:S
D
A
:I
N
T
1
]
[P
D
0
:S
C
L
:I
N
T
0
]
[D
V
S
]
[D
E
V
D
]
[D
V
D
]
[D
V
D
]
[D
V
S
:D
S
V
S
]
[P
G
5
:O
C
0
B
]
[P
G
4
:T
O
S
C
1
]
[P
G
3
:T
O
S
C
2
]
[P
D
7
:T
0
]
[P
D
6
:T
1
]
42
41
40
39
38
37
36
35
34
33
48
47
46
45
15
16
[PG1:DIG1]
[PG2:AMR]
[PB7:OC0A:OC1C:PCINT7]
[DEVDD]
44
43
29
0
30
[P
D
5
:X
C
K
1
]
[P
D
4
:I
C
P
1
]
50 49
Index corner
[D
E
V
D
]
[P
E
7
:I
C
P
3
:I
N
T
7
:C
L
K
O
]
[P
E
6
:T
3
:I
N
T
6
]
[P
E
5
:O
C
3
C
:I
N
T
5
]
[P
E
4
:O
C
3
B
:I
N
T
4
]
[P
E
3
:O
C
3
A
:A
IN
1
]
[X
T
A
L
2
]
[D
V
S
]
[P
F
1
:A
D
C
1
]
[P
F
0
:A
D
C
0
]
[A
R
E
F
]
[A
V
S
]
[A
V
D
]
[E
V
D
]
[A
V
S
:A
S
V
S
]
[X
T
A
L
1
]
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