參數資料
型號: MD80C52TXXX-16SHXXX:D
廠商: TEMIC SEMICONDUCTORS
元件分類: 微控制器/微處理器
英文描述: 8-BIT, MROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁數: 10/125頁
文件大?。?/td> 6456K
18
2486AA–AVR–02/2013
ATmega8(L)
SRAM Data
Memory
Figure 8 shows how the Atmel
AVR SRAM Memory is organized.
The lower 1120 Data memory locations address the Register File, the I/O Memory, and the inter-
nal data SRAM. The first 96 locations address the Register File and I/O Memory, and the next
1024 locations address the internal data SRAM.
The five different addressing modes for the Data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y-register or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 1024 bytes of internal data
SRAM in the ATmega8 are all accessible through all these addressing modes. The Register File
Figure 8. Data Memory Map
Register File
R0
R1
R2
R29
R30
R31
I/O Registers
$00
$01
$02
...
$3D
$3E
$3F
...
$0000
$0001
$0002
$001D
$001E
$001F
$0020
$0021
$0022
...
$005D
$005E
$005F
...
Data Address Space
$0060
$0061
$045E
$045F
...
Internal SRAM
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