參數(shù)資料
型號(hào)： MD80C52EXXX-36SHXXX
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40
封裝： CERAMIC, DIP-40
文件頁數(shù)： 323/586頁
文件大小： 25028K
代理商： MD80C52EXXX-36SHXXX
39
8272E–AVR–04/2013
ATmega164A/PA/324A/PA/644A/PA/1284/P
9.9
Timer/Counter Oscillator
Atmel ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P uses the same type of crys-
tal oscillator for Low-frequency Crystal Oscillator and Timer/Counter Oscillator. See ”Low
Frequency Crystal Oscillator” on page 35 for details on the oscillator and crystal requirements.
The device can operate its Timer/Counter2 from an external 32.768kHz watch crystal or a exter-
nal clock source. See ”Clock source connections” on page 32 for details.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
description on selecting external clock as input instead of a 32.768kHz watch crystal.
9.10
Clock Output Buffer
The device can output the system clock on the CLKO pin. To enable the output, the CKOUT
Fuse has to be programmed. This mode is suitable when the chip clock is used to drive other cir-
cuits on the system. The clock also will be output during reset, and the normal operation of I/O
pin will be overridden when the fuse is programmed. Any clock source, including the internal RC
Oscillator, can be selected when the clock is output on CLKO. If the System Clock Prescaler is
used, it is the divided system clock that is output.
9.11
System Clock Prescaler
The ATmega164A/164PA/324A/324PA/644A/644PA/1284/1284P has a system clock prescaler,
and the system clock can be divided by setting the ”CLKPR – Clock Prescale Register” on page
40. This feature can be used to decrease the system clock frequency and the power consump-
tion when the requirement for processing power is low. This can be used with all clock source
options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk
I/O,
clk
ADC, clkCPU, and clkFLASH are divided by a factor as shown in Table 9-16 on page 41.
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occurs in the clock system. It also ensures that no intermediate frequency is higher than
neither the clock frequency corresponding to the previous setting, nor the clock frequency corre-
sponding to the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU's clock frequency. Hence, it is not possible to determine the
state of the prescaler - even if it were readable, and the exact time it takes to switch from one
clock division to the other cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 × T2 before the new clock frequency is active. In this
interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the
period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1.
Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
CLKPR to zero.
2.
Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
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