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參數(shù)資料
| 型號(hào)： | MD80C52EXXX-20SHXXX |
| 廠商： | ATMEL CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 154/182頁(yè) |
| 文件大?。?/td> | 2994K |
| 代理商： | MD80C52EXXX-20SHXXX |
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73
1477K–AVR–08/10
ATtiny26(L)
A compare match will set the compare interrupt flag OCF1A after a synchronization delay follow-
ing the compare event.
Timer/Counter1
Output Compare
RegisterB – OCR1B
The Output Compare Register B is an 8-bit read/write register.
The Timer/Counter Output Compare Register B contains data to be continuously compared with
Timer/Counter1. Actions on compare matches are specified in TCCR1A. A compare match does
only occur if Timer/Counter1 counts to the OCR1B value. A software write that sets TCNT1 and
OCR1B to the same value does not generate a compare match.
A compare match will set the compare interrupt flag OCF1B after a synchronization delay follow-
ing the compare event.
Timer/Counter1
Output Compare
RegisterC – OCR1C
The Output Compare Register C is an 8-bit read/write register.
The Timer/Counter Output Compare Register C contains data to be continuously compared with
Timer/Counter1. A compare match does only occur if Timer/Counter1 counts to the OCR1C
value. A software write that sets TCNT1 and OCR1C to the same value does not generate a
compare match.
If the CTC1 bit in TCCR1B is set, a compare match will clear TCNT1 and set an Overflow Inter-
rupt Flag (TOV1). The flag is set after a synchronization delay following the compare event.
This register has the same function in normal mode and PWM mode.
PLL Control and
Status Register –
PLLCSR
Bit 7..3 – Res: Reserved Bits
These bits are reserved bits in the ATtiny26(L) and always read as zero.
Bit 2 – PCKE: PCK Enable
The PCKE bit change the Timer/Counter1 clock source. When it is set, the asynchronous clock
mode is enabled and fast 64 MHz PCK clock is used as Timer/Counter1 clock source. If this bit
is cleared, the synchronous clock mode is enabled, and system clock CK is used as
Timer/Counter1 clock source. This bit can be set only if PLLE bit is set. It is safe to set this bit
only when the PLL is locked i.e., the PLOCK bit is 1.
Bit 1 – PLLE: PLL Enable
When the PLLE is set, the PLL is started and if needed internal RC Oscillator is started as a PLL
reference clock. If PLL is selected as a system clock source the value for this bit is always 1.
Bit 0 – PLOCK: PLL Lock Detector
Bit
7
6
543
210
$2C ($4C)
MSB
LSB
OCR1B
Read/Write
R/W
Initial Value
0
Bit
7
6
543
210
$2B ($4B)
MSB
LSB
OCR1C
Read/Write
R/W
Initial Value
0
Bit
7
6
543
210
$29 ($29)
––
–––
PCKE
PLLE
PLOCK
PLLCSR
Read/Write
RR
R
R/W
R
Initial Value
0
0/1
0
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參數(shù)描述 |
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