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參數(shù)資料
| 型號(hào)： | MD80C32E-20SHXXX:D |
| 廠商： | ATMEL CORP |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 20 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | CERAMIC, DIP-40 |
| 文件頁(yè)數(shù)： | 152/234頁(yè) |
| 文件大?。?/td> | 25028K |
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24
ATtiny25/45/85 [DATASHEET]
2586Q–AVR–08/2013
6.1.4
ADC Clock – clk
ADC
The ADC is provided with a dedicated clock domain. This allows halting the CPU and I/O clocks in order to reduce
noise generated by digital circuitry. This gives more accurate ADC conversion results.
6.1.5
Internal PLL for Fast Peripheral Clock Generation - clk
PCK
The internal PLL in ATtiny25/45/85 generates a clock frequency that is 8x multiplied from a source input. By
default, the PLL uses the output of the internal, 8.0 MHz RC oscillator as source. Alternatively, if bit LSM of
PLLCSR is set the PLL will use the output of the RC oscillator divided by two. Thus the output of the PLL, the fast
peripheral clock is 64 MHz. The fast peripheral clock, or a clock prescaled from that, can be selected as the clock
source for Timer/Counter1 or as a system clock. See Figure 6-2. The frequency of the fast peripheral clock is
divided by two when LSM of PLLCSR is set, resulting in a clock frequency of 32 MHz. Note, that LSM can not be
set if PLL
CLK is used as system clock.
Figure 6-2.
PCK Clocking System.
The PLL is locked on the RC oscillator and adjusting the RC oscillator via OSCCAL register will adjust the fast
peripheral clock at the same time. However, even if the RC oscillator is taken to a higher frequency than 8 MHz,
the fast peripheral clock frequency saturates at 85 MHz (worst case) and remains oscillating at the maximum fre-
quency. It should be noted that the PLL in this case is not locked any longer with the RC oscillator clock. Therefore,
it is recommended not to take the OSCCAL adjustments to a higher frequency than 8 MHz in order to keep the PLL
in the correct operating range.
The internal PLL is enabled when:
The PLLE bit in the register PLLCSR is set.
The CKSEL fuse is programmed to ‘0001’.
The CKSEL fuse is programmed to ‘0011’.
The PLLCSR bit PLOCK is set when PLL is locked.
Both internal RC oscillator and PLL are switched off in power down and stand-by sleep modes.
6.1.6
Internal PLL in ATtiny15 Compatibility Mode
Since ATtiny25/45/85 is a migration device for ATtiny15 users there is an ATtiny15 compatibility mode for back-
ward compatibility. The ATtiny15 compatibility mode is selected by programming the CKSEL fuses to ‘0011’.
In the ATtiny15 compatibility mode the frequency of the internal RC oscillator is calibrated down to 6.4 MHz and the
multiplication factor of the PLL is set to 4x. See Figure 6-3. With these adjustments the clocking system is
ATtiny15-compatible and the resulting fast peripheral clock has a frequency of 25.6 MHz (same as in ATtiny15).
1/2
8 MHz
LSM
8.0 MHz
OSCILLATOR
PLL
8x
CKSEL[3:0]
PLLE
OSCCAL
4 MHz
1/4
LOCK
DETECTOR
PRESCALER
CLKPS[3:0]
SYSTEM
CLOCK
PLOCK
PCK
OSCILLATORS
XTAL1
XTAL2
64 / 32 MHz
8 MHz
16 MHz
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