參數(shù)資料
型號(hào)： MD80C32E-16/883
廠商： ATMEL CORP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, 16 MHz, MICROCONTROLLER, CDIP40
封裝： CERAMIC, DIP-40
文件頁數(shù)： 104/141頁
文件大小： 7628K
代理商： MD80C32E-16/883
35
2486AA–AVR–02/2013
ATmega8(L)
Standby Mode
When the SM2..0 bits are 110 and an external crystal/resonator clock option is selected, the
SLEEP instruction makes the MCU enter Standby mode. This mode is identical to Power-down
with the exception that the Oscillator is kept running. From Standby mode, the device wakes up
in 6 clock cycles.
Notes:
1. External Crystal or resonator selected as clock source
2. If AS
2 bit in ASSR is set
3. Only level interrupt INT1 and INT0
Minimizing Power
Consumption
There are several issues to consider when trying to minimize the power consumption in an AVR
controlled system. In general, sleep modes should be used as much as possible, and the sleep
mode should be selected so that as few as possible of the device’s functions are operating. All
functions not needed should be disabled. In particular, the following modules may need special
consideration when trying to achieve the lowest possible power consumption.
Analog-to-Digital
Converter (ADC)
If enabled, the ADC will be enabled in all sleep modes. To save power, the ADC should be dis-
abled before entering any sleep mode. When the ADC is turned off and on again, the next
conversion will be an extended conversion. Refer to “Analog-to-Digital Converter” on page 189
for details on ADC operation.
Analog Comparator
When entering Idle mode, the Analog Comparator should be disabled if not used. When entering
ADC Noise Reduction mode, the Analog Comparator should be disabled. In the other sleep
modes, the Analog Comparator is automatically disabled. However, if the Analog Comparator is
set up to use the Internal Voltage Reference as input, the Analog Comparator should be dis-
abled in all sleep modes. Otherwise, the Internal Voltage Reference will be enabled,
independent of sleep mode. Refer to “Analog Comparator” on page 186 for details on how to
configure the Analog Comparator.
Table 14. Active Clock Domains and Wake-up Sources in the Different Sleep Modes
Active Clock Domains
Oscillators
Wake-up Sources
Sleep
Mode
clk
CPU
clk
FLASH
clk
IO
clk
ADC
clk
ASY
Main Clock
Source Enabled
Timer Osc.
Enabled
INT1
INT0
TWI
Address
Match
Timer
2
SPM/
EEPROM
Ready
ADC
Other
I/O
Idle
X
XX
X
ADC Noise
Reduction
XX
X
XX
X
Power
Down
X
Power
Save
Standby(1)
XX(3)
X
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