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ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
when an external clock source is selected the counter counts both clock edges. In this case the counter counts the
number of edges, and not the number of bits. The clock can be selected from three different sources: The USCK
pin, Timer/Counter0 Compare Match or from software.
The Two-wire clock control unit can generate an interrupt when a start condition is detected on the Two-wire bus. It
can also generate wait states by holding the clock pin low after a start condition is detected, or after the counter
overflows.
21.3
Functional Descriptions
21.3.1
Three-wire Mode
The USI Three-wire mode is compliant to the Serial Peripheral Interface (SPI) mode 0 and 1, but does not have the
slave select (SS) pin functionality. However, this feature can be implemented in software if necessary. Pin names
used by this mode are: DI, DO, and USCK.
Figure 21-2. Three-wire Mode Operation, simplified diagram.
two Shift Registers are interconnected in such way that after eight USCK clocks, the data in each register are inter-
changed. The same clock also increments the USI’s 4-bit counter. The Counter Overflow (interrupt) Flag, or
USIOIF, can therefore be used to determine when a transfer is completed. The clock is generated by the Master
device software by toggling the USCK pin via the PORT Register or by writing a one to the USITC bit in USICR.
Figure 21-3. Three-wire Mode, timing diagram.
SLAVE
MASTER
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DO
DI
USCK
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DO
DI
USCK
PORTxn
MSB
654321
LSB
1
2
3
4
5
6
7
8
654321
LSB
USCK
DO
DI
D
C
B
A
E
CYCLE ( Reference )