參數(shù)資料
型號(hào): MCZ33996EKR2
廠商: 飛思卡爾半導(dǎo)體(中國(guó))有限公司
英文描述: 16-Output Switch with SPI Control
中文描述: 16輸出帶有SPI控制開(kāi)關(guān)
文件頁(yè)數(shù): 7/23頁(yè)
文件大小: 306K
代理商: MCZ33996EKR2
Analog Integrated Circuit Device Data
Freescale Semiconductor
7
33996
ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 4. DYNAMIC ELECTRICAL CHARACTERISTICS
Characteristics noted under conditions of 3.1 V
SO
PWR
5.5 V, 5.0 V
V
PWR
18 V, -40
°
C
T
A
125
°
C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with V
PWR
= 13 V, T
A
= 25
°
C.
Characteristic
Symbol
Min
Typ
Max
Unit
POWER OUTPUT TIMING (VPWR)
Output Slew Rate
R
L
=
60
(15)
SR
1.0
2.0
10
V/
μ
s
Output Turn ON Delay Time
(16)
t
DLY
(on)
1.0
2.0
10
μ
s
Output Turn OFF Delay Time
(16)
t
DLY
(off)
1.0
4.0
10
μ
s
Output ON Short Fault Disable Report Delay
(17)
DLY
(short)
100
450
μ
s
Output OFF Open Fault Delay Time
(17)
t
DLY
(open)
100
450
μ
s
Output PWM Frequency
t
FREQ
2.0
kHz
DIGITAL INTERFACE TIMING
(CS, SO, SI, SCLK)
(23)
Required Low State Duration on V
PWR
for Reset
V
PWR
0.2 V
(18)
t
RST
10
μ
s
Falling Edge of
CS
to Rising Edge of SCLK
Required Setup Time
t
LEAD
100
ns
Falling Edge of SCLK to Rising Edge of CS
Required Setup Time
t
LAG
50
ns
SI to Falling Edge of SCLK
Required Setup Time
t
SI
(
su
)
16
ns
Falling Edge of SCLK to SI
Required Hold Time
t
SI
(
hold
)
20
ns
SI,
CS
, SCLK Signal Rise Time
(19)
t
R
(SI)
5.0
ns
SI,
CS
, SCLK Signal Fall Time
(19)
t
F
(SI)
5.0
ns
Time from Falling Edge of
CS
to SO Low Impedance
(20)
t
SO
(
en
)
50
ns
Time from Rising Edge of
CS
to SO High Impedance
(21)
t
SO
(
dis
)
50
ns
Time from Rising Edge of SCLK to SO Data Valid
(22)
t
VALID
25
80
ns
Notes
15.
16.
17.
18.
19.
20.
21.
22.
23.
Output slew rate measured across a
60
resistive load.
Output turn ON and OFF delay time measured from 50% rising edge of
CS
to 80% and 20% of initial voltage.
Duration of fault before fault bit is set. Duration between access times must be greater than 450
μ
s to read faults.
This parameter is guaranteed by design; however, it is not production tested.
Rise and Fall time of incoming SI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO pin.
Time required for output states data to be terminated at SO pin.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
This parameter is guaranteed by design. Production test equipment used 4.16 MHz, 5.5 V/3.1 V SPI Interface.
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