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參數(shù)資料
| 型號(hào)： | MCZ33993EW |
| 廠商： | 飛思卡爾半導(dǎo)體(中國(guó))有限公司 |
| 英文描述： | Multiple Switch Detection Interface |
| 中文描述： | 多交換檢測(cè)接口 |
| 文件頁(yè)數(shù)： | 6/28頁(yè) |
| 文件大?。?/td> | 504K |
| 代理商： | MCZ33993EW |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
6
33993
ELECTRICAL CHARACTERISTICS
STATIC ELECTRICAL CHARACTERISTICS
DIGITAL INTERFACE
Input Logic Voltage Thresholds
(9)
V
INLOGIC
0.8
–
2.2
V
SCLK, SI, Tri-State SO Input Current
0 V to V
DD
I
SCLK,
I
SI,
I
SO (TRI)
-10
–
10
μ
A
CS
Input Current
CS
= V
DD
I
CS
-10
–
10
μ
A
CS
Pull-Up Current
CS
= 0 V
I
CS
30
–
100
μ
A
SO High-State Output Voltage
I
SO (
HIGH)
= -200
μ
A
V
SO (
HIGH)
V
DD
- 0.8
–
V
DD
V
SO Low-State Output Voltage
I
SO (
HIGH)
= 1.6 mA
V
SO (
LOW)
–
–
0.4
V
Input Capacitance on SCLK, SI, Tri-State SO
(10)
C
IN
–
–
20
pF
INT
Internal Pull-Up Current
–
15
40
100
μ
A
INT
Voltage
INT
= Open Circuit
V
INT
(
HIGH
)
V
DD
- 0.5
–
V
DD
V
INT Voltage
I
NT
= 1.0 mA
V
INT
(LOW)
–
0.2
0.4
V
WAKE
Internal Pull-Up Current
I
WAKE
(
PU
)
20
40
100
μ
A
WAKE
Voltage
WAKE
= Open Circuit
V
WAKE
(
HIGH
)
4.0
4.3
5.3
V
WAKE
Voltage
I
WAKE
= 1.0 mA
V
WAKE
(
LOW
)
–
0.2
0.4
V
WAKE
Voltage
Maximum Voltage Applied to
WAKE
Through External Pull-Up
V
WAKE
(
MAX
)
–
–
40
V
Notes
9.
10.
Upper and lower logic threshold voltage levels apply to SI,
CS
, and SCLK.
This parameter is guaranteed by design but is not production tested.
Table 3. Static Electrical Characteristics (continued)
Characteristics noted under conditions 3.1 V
≤
V
DD
≤
5.25 V, 8.0 V
≤
V
PWR
≤
16 V, -40
°
C
≤
T
C
≤
125
°
C, unless otherwise
noted. Typical values noted reflect the approximate parameter means V
PWR
= 13 V, T
A
= 25
°
C under nominal conditions unless
otherwise noted.
Characteristic
Symbol
Min
Typ
Max
Unit
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