CAN INTERFACE DESCRIPTION Figure 35. Single Dominant " />
參數(shù)資料
型號: MCZ33905BD3EK
廠商: Freescale Semiconductor
文件頁數(shù): 60/106頁
文件大小: 0K
描述: IC SBC CAN HS 3.3V 54SOIC
標(biāo)準(zhǔn)包裝: 26
應(yīng)用: 系統(tǒng)基礎(chǔ)芯片
接口: CAN,LIN
電源電壓: 5.5 V ~ 28 V
封裝/外殼: 54-SSOP(0.295",7.50mm 寬)裸露焊盤
供應(yīng)商設(shè)備封裝: 54-SOICW-EP
包裝: 管件
安裝類型: 表面貼裝
Analog Integrated Circuit Device Data
Freescale Semiconductor
57
33903/4/5
CAN INTERFACE
CAN INTERFACE DESCRIPTION
Figure 35. Single Dominant Pulse Wake-up
Pattern Wake-up
In order to Wake-up the CAN interface, the Wake-up
receiver must receive a series of three consecutive valid
dominant pulses, by default when the CANWU bit is low.
CANWU bit can be set high by SPI and the Wake-up will occur
after a single pulse duration of 2.0
s (typically).
A valid dominant pulse should be longer than 500 ns. The
three pulses should occur in a time frame of 120
s, to be
considered valid. When three pulses meet these conditions,
the wake signal is detected. This is illustrated by the following
figure.
.
Figure 36. Pattern Wake-up - Multiple Dominant Detection
BUS TERMINATION
The device supports the two main types of bus
terminations:
Differential termination resistors between CANH and
CANL lines.
SPLIT termination concept, with the mid point of the
differential termination connected to GND through a
capacitor and to the SPLIT pin.
In application, the device can also be used without
termination.
Figure 37 illustrates some of the most common
terminations.
CANL
CANH
Internal Wake-up signal
Dominant
CAN
Pulse # 1
Dominant
Pulse # 2
tCAN WU1-F
Can Wake-up detected
bus
Internal differential Wake-up receiver signal
CANL
CANH
Internal Wake-up signal
Dominant
Internal differential Wake-up receiver signal
CAN
Pulse # 1
Dominant
Pulse # 2
Dominant
Pulse # 3
Dominant
Pulse # 4
tCAN WU3-F
tCAN WU3-TO
Dominant Pulse # n: duration 1 or multiple dominant bits
Can Wake-up detected
bus
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