OPERATIONAL MODES FUNCTIONAL DEVICE OPERATI" />
參數(shù)資料
型號(hào)： MCZ33797EKR2
廠商： Freescale Semiconductor
文件頁(yè)數(shù)： 13/36頁(yè)
文件大?。?/td> 0K
描述： IC SQUIB DRIVER 2CHAN 32-SOIC
標(biāo)準(zhǔn)包裝： 1,000
系列： *
應(yīng)用： *
接口： *
電源電壓： *
封裝/外殼： 32-SOIC（0.295"，7.50mm 寬）
供應(yīng)商設(shè)備封裝： 32-SOIC
包裝： 帶卷 (TR)
安裝類型： 表面貼裝
Analog Integrated Circuit Device Data
20
Freescale Semiconductor
33797
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
FUNCTIONAL DEVICE OPERATION
OPERATIONAL MODES
INTRODUCTION
In this section references are made to XX; e.g., in
SQB_HI_XX, SQB_LO_XX, and SENSE_XX pins.
SQB_HI_XX refers to SQB_HI_1A, SQB_HI_1B,
SQB_HI_2A or SQB_HI_2B, SQB_LO_1A, etc.
SERIAL INTERFACE
An 8-bit shift register is provided for communication through
the serial port to a microprocessor. The four wire SPI
interface is used to read from, and write to, the shift register.
Data written to the shift register will control the firing of the
FET switches or select a diagnostic mode. Data is
sequentially shifted into and out of the shift register, most
significant bit first.
Data read from the shift register will contain the results of the
diagnostic mode selected in the previous 8-bit write. If a NOP
command is written, all diagnostic modes are cleared and the
data in the shift registers will be read out. With any undefined
commands, all diagnostic modes are cleared and the data in
the shift registers will be read out. All functions are set when
CS goes high. All diagnostic commands are cleared on the
next valid SPI command.
SPI INTERFACE INTEGRITY CHECK
The $96 command with corresponding $69 return byte during
the next 8-bit write is used as an echo function to diagnose
the SPI integrity (refer to Table 9).
The Diagnostic Data Out bits not containing data are set to
zero.
Only 8-bit words will be accepted. Any words that are
7 bits
or
9 bits will be ignored or cleared.
The second byte for command programming will be treated
as a NOP if any FET is firing. The programming commands
must be sequential or they will be treated as a NOP.
The four channel squib driver IC is a slave peripheral device
designed to interface to a Freescale SPI or other serial
peripheral interface. Data is read on the rising edge of CLK,
and data is transferred out on the rising edge of CLK. On the
falling edge of CS, the IC configures itself for one of two SPI
modes. If CLK is low, the IC will configure itself to be in
Freescale SPI mode (see Figure 5). If CLK is high, the IC will
configure itself to be in an alternative SCI mode (see
Figure 5). In both cases, data is still read off the rising edge
and transferred off the falling edge of the CLK. When the IC
is deselected (CS goes high), then D0 is a high-impedance
output.
Response bit 7 of command $C8 (refer to Table 8, page 24)
is hard-wired to “1” or “0” to identify the squib IC as a four or
two channel squib driver IC. When a $C8 command is issued
for the four channel squib driver IC, the response bit 7 is set
to a “0”. When a $C8 command is issued for the two channel
squib driver IC, the response bit 7 is set to a “1”.
STANDARD SQUIB IC FUNCTION
The standard squib IC application utilizes the high and low
side squib drivers from the same squib driver ICs (see
Figure 6, Standard Squib Firing).
The SENSE_XX (1A, 1B, 2A, 2B) pin is connected to
SQB_LO_XX (1A, 1B, 2A, 2B). Squib diagnostics are
conducted using this pin. In the standard mode, the $C2
(SQUIB_LO_XX_CONT) command will be used to check
continuity of the low side driver from the SQB_LO_XX pin
(1A, 1B, 2A, 2B) to the low side driver FET (Figure 6).
The low side driver continuity is checked during the continuity
test. The driver continuity information will be cleared after the
information is transmitted on the next valid SPI command.
EXAMPLE—STANDARD SQUIB COMMAND SPI
SEQUENCE FROM MICROCONTROLLER
TX: Request squib short-to-battery/GND diagnostic mea-
surement ($C1).
RX: Previous executed command information.
TX: Request squib 1A resistance measurement
($D0–$D3).
RX: Receive results from short-to-battery/GND diagnos-
tics.
TX: Request squib 1B resistance measurement
($D0–$D3).
RX: Receive measured squib 1A resistance information.
TX: Request squib 2A resistance measurement
($D0–$D3).
RX: Receive measured squib 1B resistance information.
TX: Request squib 2B resistance measurement
($D0–$D3).
RX: Receive measured squib 2A resistance information
TX: Request continuity command ($C2).
RX: Receive measured squib 2B resistance information
TX: Request another command sequence.
RX: Receive low side driver 1A, 1B, 2A, and 2B continuity
information. Latches will be cleared after data trans-
ferred from the squib IC (clear on rising edge of chip
select).
TX: Request loop-to-loop short command ($E0–$E3)
RX: Previous executed command information.
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